csee4824_f11_lec15-1

csee4824_f11_lec15-1 - CSEE W4824 Computer Architecture...

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon
1 CSEE W4824 – Computer Architecture Fall 2011 Luca Carloni Department of Computer Science Columbia University in the City of New York http://www.cs.columbia.edu/~cs4824/ Lecture 15 Memory Hierarchy Design: Virtual Memory CSEE 4824 – Fall 2011 - Lecture 15 Page 2 Luca Carloni – Columbia University Review: Extendint Tomasulo’s Algorithm to Handle Speculation • Reorder Buffer (ROB) – completely replaces the store buffer • stores still execute in two steps, but the second step is performed by instruction commits – takes over the renaming function from reservation stations • reservation stations still provide buffering for operations and operands each issued instruction has a ROB entry until it commits • ROB entry, and not reservation station, is used to tag the instruction result
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2 Speculative Tomasulo’s Alg.: Checking & Bookkeeping per Instruction ( op D,S1,S2 ) f (if (RS[ f ].Qj == RS[ r]. robTag) RS[ f ].Vj res ; RS[ f ].Qj 0 ) f (if (RS[ f ].Qk == RS[ r]. robTag) RS[ f ].Vk res ; RS[ f ].Qk 0 ) RS[ r ].busy no; ROB[RS[ r]. robTag].val res ; ROB[RS[ r]. robTag].ready yes RS.[ r ] is done & CDB is available 3. Write Result if (Regs[ROB[ b ].des].robTag == b ) { Regs[ROB[ b ].des].value ROB[ b ].val; Regs[ROB[ b ].des].robTag 0 } ROB[ b ].ins ←∅ ROB.[ b ] @ head of ROB ROB.[ b ].ready == yes 4. Commit execute operation using operands in RS[ r ].Vj and RS[ r ].Vk and producing res (RS.[ r ].Qj == 0) and (RS.[ r ].Qk == 0) 2. Execute if ( ( h = Regs[ S1 ] . robTag) 0)) { if (ROB[ h ].ready) RS.[ r ].Vj ROB[ h ].val else RS[ r ].Qj h }e lse RS.[ r ].Vj Regs[ S1 ].value if ( ( h = Regs[ S2 ] . robTag) 0)) { if (ROB[ h ].ready) RS.[ r ].Vk ROB[ h ].val else RS[ r ].Qk h RS.[ r ].Vk Regs[ S1 ].value RS[ r ].busy yes ; RS[ r ].robTag b ; Regs( D) .robTag b ; ROB[ b ].ins op ; ROB[ b ].des D ; ROB[ b ].ready no; (RS[ r ].busy == no) where r is the reservation station for the functional unit matching op b (ROB[ b ].ins == ) 1. Issue Bookkeeping Wait until Inst. Status CSEE 4824 – Fall 2011 - Lecture 15 Page 4 Luca Carloni – Columbia University Announcements •M id t e rm : Monday, October 31 In class, 75 minutes – OPEN BOOK and OPEN NOTES – NO ELECTRONIC EQUIPMENT MAY BE USED – Material covered by the midterm FROM LECTURE #1 UNTIL LECTURE #12 INCLUDED • Special Session: Midterm Review – Friday 10/28 from 12:30pm to 2:15pm in 833 Mudd – TAs will lead the session by discussing the solution of the practice midterm and answering general questions
Background image of page 2
3 CSEE 4824 – Fall 2011 - Lecture 15 Page 5 Luca Carloni – Columbia University Announcements •S ch ed u l e C h a n g e – The office hour of TA Sumedh Attarde for Monday 10/31 is moved to Friday 10/28 from 10am to 12noon CSEE 4824 – Fall 2011 - Lecture 15 Page 6 Luca Carloni – Columbia University Review: Giving the Illusion of Unlimited, Fast Memory: Exploiting Memory Hierarchy • Principle of Locality • Smaller HW is typically faster • All data in one level are usually found also in the level below Technology SRAM DRAM Magnetic Disk 2008 Cost ($/GB) $2000-$5000 $20-$75 $0.2-$2 Bandwidth 20-100 GB/sec 5-10 GB/sec 1-5 GB/sec 20-150 MB/sec 0.5 – 2.5 ns 50 – 70 ns 5ms Energy per Access 1nJ 1-100nJ (per device) 100-1000mJ
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
4
Background image of page 4
Image of page 5
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 15

csee4824_f11_lec15-1 - CSEE W4824 Computer Architecture...

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online