{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

csee4824_f11_lec18

csee4824_f11_lec18 - CSEE W4824 Computer Architecture Fall...

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon
1 CSEE W4824 – Computer Architecture Fall 2011 Luca Carloni Department of Computer Science Columbia University in the City of New York http://www.cs.columbia.edu/~cs4824/ Lecture 18 Overview of Parallel Architectures and Interconnection Networks CSEE 4824 – Fall 2011 - Lecture 18 Page 2 Luca Carloni – Columbia University Review: Processor Clock-Rate Growth and Its Impact on the Overall Performance Between 1978 and 1986, clock rate improved less than 15% per year while performance improved by 25% Between 1986 and 2003, clock rate improved by ~40% per year while performance improved by 52% Since 2003, clock rate has been growing less than 1% per year, while single processor performance improved at less than 22% per year
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
2 CSEE 4824 – Fall 2011 - Lecture 18 Page 3 Luca Carloni – Columbia University Review: “Chips are Power Limited: Most Power is Spent Moving Data” (B. Dally, DAC 2009) CSEE 4824 – Fall 2011 - Lecture 18 Page 4 Luca Carloni – Columbia University Review: Challenges and Opportunities with The Rise of Multi-Core Architectures State-of-the-art commercial chips feature more parallel, distributed and heterogeneous architectures (multi- core chips) Intel Sandy Bridge IBM WireSpeed SoC Parallel architectures with multiple simpler processing cores provide better performance per watt than systems based on a single complex processor New issues software plays an increasingly important role in ESL design (programming models, load balancing, power management) new sources of design uncertainty at the system-level because the behavior of OS and interrupt routines is more difficult to model as it varies over time bus-based communication does not scale necessary to design robust, scalable, fast, and power-efficient intra-chip communication networks
Background image of page 2
3 CSEE 4824 – Fall 2011 - Lecture 18 Page 5 Luca Carloni – Columbia University communication abstraction programming models parallel applications Parallel Computer Architecture and Abstraction Layers big gap physical communication medium communication hardware multiprogramming CAD Database Scientific Modeling shared address message passing compilation or library user/system boundary OS support CSEE 4824 – Fall 2011 - Lecture 18 Page 6 Luca Carloni – Columbia University Flynn Taxonomy of Computer Architectures (1972) based on parallelism of instruction streams and data streams • SISD single instruction stream, single data stream • microprocessors • SIMD single instruction stream, multiple data streams vector processors; principle behind multimedia extensions • MISD multiple instruction streams, single data stream not commercial processors (yet) • MIMD multiple instruction streams, multiple data streams each processor fetches its own instruction and operates on its own data
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon