borkenhager00_powerPcMultithreaded

borkenhager00_powerPcMultithreaded - A multithreaded...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
by J. M. Borkenhagen R. J. Eickemeyer R. N. Kalla S. R. Kunkel A multithreaded PowerPC processor for commercial servers This paper describes the microarchitecture of the RS64 IV, a multithreaded PowerPC ® processor, and its memory system. Because this processor is used only in IBM iSeries TM and pSeries TM commercial servers, it is optimized solely for commercial server workloads. Increasing miss rates because of trends in commercial server applications and increasing latency of cache misses because of rapidly increasing clock frequency are having a compounding effect on the portion of execution time that is wasted on cache misses. As a result, several optimizations are included in the processor design to address this problem. The most significant of these is the use of coarse-grained multithreading to enable the processor to perform useful instructions during cache misses. This provides a significant throughput increase while adding less than 5% to the chip area and having very little impact on cycle time. When compared with other performance- improvement techniques, multithreading yields an excellent ratio of performance gain to implementation cost. Second, the miss rate of the L2 cache is reduced by making it four-way associative. Third, the latency of cache-to- cache movement of data is minimized. Fourth, the size of the L1 caches is relatively large. In addition to addressing cache misses, pipeline “holes” caused by branches are minimized with large instruction buffers, large L1 I-cache fetch bandwidth, and optimized resolution of the branch direction. In part, the branches are resolved quickly because of the short but efficient pipeline. To minimize pipeline holes due to data dependencies, the L1 D-cache access is optimized to yield a one-cycle load- to-use penalty. 1. Introduction This paper describes the microarchitecture of a multithreaded PowerPC* processor and its memory system that has been optimized for server workloads. Code- named SStar, this processor is known externally as the RS64 IV in the pSeries* 6000 (previously RS/6000*). It became available for purchase in the fourth quarter of r Copyright 2000 by International Business Machines Corporation. Copying in printed form for private use is permitted without payment of royalty provided that (1) each reproduction is done without alteration and (2) the Journal reference and IBM copyright notice are included on the first page. The title and abstract, but no other portions, of this paper may be copied or distributed royalty free without further permission by computer-based and other information-service systems. Permission to republish any other portion of this paper must be obtained from the Editor. 0018-8646/00/$5.00 © 2000 IBM IBM J. RES. DEVELOP. VOL. 44 NO. 6 NOVEMBER 2000 J. M. BORKENHAGEN ET AL.
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 14

borkenhager00_powerPcMultithreaded - A multithreaded...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online