horowitzDally_isscc2004

horowitzDally_isscc2004 - ISSCC 2004 / SESSION 7 / TD:...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ISSCC 2004 / SESSION 7 / TD: SCALING TRENDS / 7.1 7.1 How Scaling Will Change Processor Architecture Mark Horowitz, William Dally Stanford University, Stanford, CA For the past two decades, microprocessors have doubled in per- formance every 18-24 months (Fig. 7.1.1) without substantial changes to the underlying instruction-set architecture (ISA). However, for performance to continue to scale over the coming decade, significant architectural changes are required since improvements in two of the three factors that have historically driven processor performance, ILP (Fig. 7.1.2) and gates per clock (Fig. 7.1.3), have essentially reached their limit. The third factor, process technology, is also driving architectural change as it becomes wire and power limited rather than device limited. Future architectures will employ explicit parallelism to compen- sate for flat ILP, feature modularity to minimize the use of glob- al wires, and exploit locality and heterogeneous architectures for power efficiency. Fortunately most emerging applications have large amounts of explicit task and data-level parallelism and can be mapped to these new architectures. Unfortunately, even in these new machines, power constraints limit achievable perform- ance. Historically scaling technology by reduced the switching ener- gy of each gate by 3 (capacitance and voltage both scale down); overall processor power, nevertheless, grew exponentially reach- ing over 100W today. Power increased because processors scale frequency as 1/ 2 , which counters the effect of voltage scaling, and have increased complexity. Consequently, total capacitance scales up not down. The power of todays chips is now limited by the cost of the cooling. A power constrained environment completely changes the approach to processor design. Rather than looking for the fastest implementations, one has to look for the most energy efficient implementations, since the highest performance implementation dissipates too much power. Designers must find the performance enhancements with the lowest marginal energy cost. In fact, in an optimal machine the marginal energy cost for a change in per- formance is the same for each of the tuning variables available to the designer, whether it be Vdd, Vth, transistor W, circuit style, microarchitecture, or exploiting parallelism [1]....
View Full Document

Page1 / 8

horowitzDally_isscc2004 - ISSCC 2004 / SESSION 7 / TD:...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online