hw3 - CSEE W4824 Prof. Luca Carloni Homework 3 Handout 9...

Info iconThis preview shows pages 1–4. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: CSEE W4824 Prof. Luca Carloni Homework 3 Handout 9 October 12, 2011 This homework is due at the beginning of class on Wednesday, October 26. A correct answer without adequate explanation or derivation will have points deducted. To get full credit, write legibly/type, and show all work (label relevant items, show derivations, include explanations). 1. (0 points) . Read the assigned paper (handout #8 ). 2. (9 points) . Consider the following MIPS code fragment: LD R5,32(R2) SUB R9,R4,R1 ADD R8,R5,R6 AND R6, R4, R1 XOR R1, R6, R8 BNEZ R9, target OR R6, R3, R1 ADD R7, R8, R1 SD R7, 32(R2) SUB R7, R8, R9 ADD R9, R8, R1 target : LD R5, 200(R1) Do the following: (a) Identify each dependence by type. Distinguish between data dependencies, anti-dependencies, output dependencies and control dependencies. Fill out Table 1 by reporting the corresponding data for each dependence. The Storage Location column should contain the name of the storage location involved in the dependence, if there is one. (b) Assume the standard MIPS five-stage pipelined processor implementation (as described in the H&P Appendix) without optimized branch hardware. Consider the following three scenar- ios: Scenario number register read and write in the same clock cycle full forwarding logic (only forwards through the register file) 1 no no 2 yes no 3 yes yes For each of the dependencies identified in (a) determine whether it causes a hazard while exe- cuting the MIPS code fragment on the given processor implementation for each of the above 3 scenarios. Annotate the last three columns of Table 1 consequently by writing yes or no. Dependency Independent Dependent Storage Hazard ? Hazard ? Hazard ? Type Instruction Instruction Location (Scenario 1) (Scenario 2) (Scenario 3) Table 1: Table for Problem 2. 2 3. (9 points) . Consider three processors P 1 ,P 2 ,P 3 that have the same basic architecture and differ only for the cache configurations, which are respectively: Cache 1 : direct-mapped with one-word blocks for P 1 ; Cache 2 : direct-mapped with four-word blocks for P 2 ; Cache 3 : two-way set associative with eight-word blocks for P 3 . For each processor, the memory address space is 32 bits. Each cache may contain 8 K bytes of data and is byte-addressed. Assume that running a program with an instruction count IC = 10 , 000 you measured the following miss rates: Cache 1 : instruction miss rate is 5% and data miss rate is 6% ; Cache 2 : instruction miss rate is 4% and data miss rate is 4% ; Cache 3 : instruction miss rate is 2% and data miss rate is 2% ; For all processors, assume that one-half of the instructions contain a data reference and that the cache miss penalty is 6 + B cycles, where B is the block size in words....
View Full Document

Page1 / 11

hw3 - CSEE W4824 Prof. Luca Carloni Homework 3 Handout 9...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online