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Unformatted text preview: SESC: SuperESCalar Simulator Pablo Montesinos Ortego Paul Sack December 20, 2004 1 What is this all about? The biggest challenge for new students in architecture research groups is not passing theory or software classes. It is not finding a new apartment or register- ing with the INS. It is understanding the architecture of the processor simulator that will soon confront them–a simulator coded not for perfection, but for dead- lines. Even the most well-conceived simulator can quickly look like a Big Ball of Mud to the unitiated. 1.1 Typical initation procedure • Find a desk • Configure computer, email userhelp, etc. • Advisors says something like “Why don’t you start working on this?” • Bother older student for simulator access • Download source code • Find documentation • After finding that the documentation is less than useless (if it even exists), bother senior students with pesky questions • Senior students graduate • You are the most senior student • Give up, read the code • Add more mud • ... • Graduate 1 1.2 Purpose of this document This document is intended to break the chain of simulator initiation. This document explains, at a high level, the workings of the core of the simulator, the part that new students must learn first. SESC is under constant development and changes overnight, but this document describes the more permanent, stable core of the simulator. This document cannot explain all of SESC. It is a great starting point, from which the SESC novice can dive into the source code. This is the documentation we wish we had. 2 Introduction 2.1 What is a microprocessor simulator? In microarchitecture research, typically researchers have some kind of proposal for a microprocessor that will be better than the current state of the art. It might be faster, use less power, be more reliable, or create the perfect loaf of bread. In any event, since it is expensive to design and fabricate a microprocessor, researchers write microprocessor simulators. There are different approaches to this. Some are trace-driven, i.e., they use instruction traces of applications. Most are execution-driven, i.e., they actually execute the simulated application. Many simulators also divide simulation into an emulator, which actually executes the simulated application, and a timing simulator, which models the timing and energy of the simulated application. It is also common to have at least part of the simulator be event-driven. What this means is that parts of the simulator can schedule an event, i.e., a function call with parameters, to occur at some time in the future. 2.2 What is SESC? SESC is a microprocessor architectural simulator developed primarily by the i-acoma research group at UIUC and various groups at other universities that models different processor architectures, such as single processors, chip multi- processors and processors-in-memory. It models a full out-of-order pipeline with branch prediction, caches, buses, and every other component of a modern pro-...
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This note was uploaded on 11/12/2011 for the course CSEE 4824 taught by Professor Carloni during the Fall '11 term at Columbia.
- Fall '11