syllabus - WEEK#9 October 31 November 2 Thread-Level...

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CSEE W4824 Prof. Luca Carloni Tentative Syllabus Handout 2 September 7, 2011 WEEK #1: September 7 Course Introduction. WEEK #2: September 12-14 Computer design fundamentals; principle of quantitative analysis; instruction set architectures WEEK #3: September 19-21 Pipelining: review of basic concepts; implementation issues; multi-cycle operations. Case study: MIPS R4000. WEEK #4: September 26-28 Instruction-Level Parallelism: dynamic scheduling; scoreboard, Tomasulo’s algorithm. Case study: IBM 360. WEEK #5: October 3-5 Memory-Hierarchy Design: review of the basics of caches; cache optimization. Case study: Intel Itanium 2. WEEK #6: October 10-12 Instruction-Level Parallelism: branch prediction and speculation. Case study: Alpha 21264. WEEK #7: October 17-19 Memory-Hierarchy Design: virtual memory; Case study: Intel Pentium 4 vs. AMD Opteron. WEEK #8: October 24-26 Instruction-Level Parallelism: compiler techniques. VLIW architectures. MIDTERM (tentative date!): MONDAY, OCT 31st (in class). Topics covered: first seven weeks.
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Unformatted text preview: WEEK #9: October 31 - November 2 Thread-Level Parallelism: multithreaded architectures. Case study: Intel Pentium 4. WEEK #10: November 7-9 [NO CLASS 11/7: Academic Holiday] Multi-Core Architectures: chip multi-processors (CMP) and systems-on-chip (SoC). Case study: Intel Core. WEEK #11: November 14-16 Parallel Architectures: taxonomy; types of parallelism; programming and communication models. WEEK #12: November 21-23 Parallel Architectures: memory consistency model & cache coherency. WEEK #13: November 28-30 Multi-Core Architectures: embedded and mobile computing. Case Studies: ARM 11, TI OMAP platforms. WEEK #14: December 5-7 Multi-Core Architectures: cloud computing; accelerators and networks-on-chip. Case Study: IBM Wire-Speed. WEEK #15: December 12 [Final Course Review] Perspective: “Towards Thousand-Core Processors: Opportunities and Challenges.” FINAL EXAM: time & location to be announced...
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