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Unformatted text preview: transistors needed to implement each design. 5. Find a circuit using the minimum number of 4-input LUTs that implements the three logic functions, below: X = (A + DF’)(BC + BC’E) Y = (B’+C’E’) + (A’D + AD’ + DF) Z = AB(C + E)(D’ + A’F) 6. For the following circuit, assume all gates have a minimum propagation delay of 2 ns and a maximum delay of 3 ns (for both rising and falling edges). Construct a timing diagram showing the time periods where the output could be either 0 or 1 (and, thus is unknown) when B=1 and C=0. Shade this region of your diagram. 7. For the following truth table, construct a circuit with the least delay and also one with the smallest gate count. Use only inverters, 2-input AND and 2-input OR gates. Assume each inverter has a 1 ns delay and each AND/OR gate has a 2 ns delay. Digital Logic Homework University of Information Technology - Computer Engineering Faculty Page 3 When counting gates, each AND/OR is one (1) and each inverter is ½....
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- Spring '11
- Boolean Algebra, Logic gate, Boolean function, Logical connective