Homework7

# Homework7 - Homework7(Due 1 Draw a timing diagram for the...

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Digital Logic Homework University of Information Technology - Computer Engineering Faculty Page 1 Homework7 (Due November 15, 2010) 1. Draw a timing diagram for the following NOR circuit for an SR latch with the following input changes. Assume a 2.5 ns delay for each gate. Comment on why we don’t let S=R=1 on a latch. Show your timing diagram to at least 60 ns.

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Digital Logic Homework University of Information Technology - Computer Engineering Faculty Page 2 2. Assume that each flip-flop has a setup time of 2 ns, a hold time of 3 ns and a clock-to-output delay of 5 ns. Further assume that each gate has a delay of 2 ns except each inverter has a delay of 1 ns. What is the maximum clock frequency that you can clock the following circuits. Also discuss what constraints are placed on the inputs.
Digital Logic Homework University of Information Technology - Computer Engineering Faculty Page 3 3. For the following storage device, derive the state transition diagram (bubble diagram) and find the next-state, or characteristic, equation (note the outputs are complements of each other).

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• Spring '11
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Homework7 - Homework7(Due 1 Draw a timing diagram for the...

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