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Unformatted text preview: combinational circuit components: (a) an 8 bit addersubtractor with C in and C out ; (b) A binary multiplier that multiplies two 8bit numbers; (c) a code converter from a 4digit BCD number to a binary number. 4. A 32K×8 RAM chip uses coincident decoding by splitting the internal decoder into row select and column select. (a) Assuming that the RAM cell array is square, what is the size of each decoder, and how many Digital Logic Homework University of Information Technology  Computer Engineering Faculty Page 2 AND gates are required for decoding an address? (b) Determine the row and column selection lines that are enabled when the input address is the binary equivalent of 21000 10 . 5. A DRAM has a refresh interval of 128 ms and has 4096 rows. What is the interval between refreshes for distributed refresh? What is the minimum number of address pins on the DRAM?...
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This note was uploaded on 11/13/2011 for the course ECON 1 taught by Professor Khai during the Spring '11 term at MIT.
 Spring '11
 KHAI

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