c09samp4 - Section 9.2 Design Examples Using VHDL 825 DO...

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Section 9.2 Design Examples Using VHDL 825 DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY Copyright © 1999 by John F. Wakerly Copying Prohibited The program in Table 9-21 does not specify a state assignment; a typical synthesis engine will use three bits for Sreg and assign the six states in order to binary combinations 000–101. For this state machine, it is also possible to use an output coded state assignment, using just the lamp and error output signals that are already required. VHDL does not provide a convenient mechanism for grouping together the entity’s existing output signals and using them for state, but we can still achieve the desired effect with the changes shown in Table 9-22. Here we used a comment to document the correspondence between outputs and the bits of the new, 5-bit Sreg , and we changed each of the output assignment statements to pick off the appropriate bit instead of fully decoding the state. 9.2.4 Reinventing Traffic-Light Controllers If you read the ABEL example in Section 9.1.5, then you’ve already heard me rant about the horrible traffic light controllers in Sunnyvale, California. They really do seem to be carefully designed to maximize the waiting time of cars at intersections. In this section we’ll design a traffic-light controller with distinctly Sunnyvale-like behavior. An infrequently used intersection (one that would have no more than a “yield” sign if it were in Chicago) has the sensors and signals shown in architecture Vggameoc_arch of Vggame is signal Sreg: STD_LOGIC_VECTOR (1 to 5); -- bit positions of output-coded assignment: L1, L2, L3, L4, ERR constant S1: STD_LOGIC_VECTOR (1 to 5) := "10000"; constant S2: STD_LOGIC_VECTOR (1 to 5) := "01000"; constant S3: STD_LOGIC_VECTOR (1 to 5) := "00100"; constant S4: STD_LOGIC_VECTOR (1 to 5) := "00010"; constant SERR: STD_LOGIC_VECTOR (1 to 5) := "00001"; constant SOK: STD_LOGIC_VECTOR (1 to 5) := "00000"; begin process (CLOCK) ... (no change to process) end process; L1 <= Sreg(1); L2 <= Sreg(2); L3 <= Sreg(3); L4 <= Sreg(4); ERR <= Sreg(5); end Vggameoc_arch; Table 9-22 VHDL architecture for guessing game using output-coded state assignment.
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826 Chapter 9 Sequential-Circuit Design Examples DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY Copyright © 1999 by John F. Wakerly Copying Prohibited Table 9-23 VHDL program for Sunnyvale traffic-light controller. library IEEE; use IEEE.std_logic_1164.all; entity Vsvale is port ( CLOCK, RESET, NSCAR, EWCAR, TMSHORT, TMLONG: in STD_LOGIC; OVERRIDE, FLASHCLK: in STD_LOGIC; NSRED, NSYELLOW, NSGREEN: out STD_LOGIC; EWRED, EWYELLOW, EWGREEN, TMRESET: out STD_LOGIC ); end; architecture Vsvale_arch of Vsvale is type Sreg_type is (NSGO, NSWAIT, NSWAIT2, NSDELAY, EWGO, EWWAIT, EWWAIT2, EWDELAY); signal Sreg: Sreg_type;
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This note was uploaded on 11/14/2011 for the course DDDD h0322 taught by Professor Whoknow during the Spring '11 term at Bina Nusantara University.

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c09samp4 - Section 9.2 Design Examples Using VHDL 825 DO...

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