DesignProject - ECE/CS 5720/6720 Design Project Op-Amp...

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ECE/CS 5720/6720 Design Project – Op-Amp Design Due Friday, April 4 by 6:00 pm. In this project, you will design, lay out, and simulate a high-performance operational amplifier. Your op-amp must meet the following minimum performance specifications while driving a load of C L = 15 pF: A unity-gain frequency ( f t ) of 300 kHz or greater. A low-frequency gain of 72 dB or greater. A phase margin of at least 60 ° . A power dissipation of 16 mW or less. An input common-mode range (ICMR) and output common-mode range (OCMR) of ±1V, with no visible distortion of signals between these values. A positive and negative slew rate of 0.2 V/ μ s or greater. Your op-amp must be constructed under the following constraints: A layout that fits within a 220 μ m × 220 μ m square. The 15-pF load capacitor C L should not be included in your layout, and should only be included in your simulation, as this represents an external load. While common-centroid layout is generally a good idea for differential pair transistors in op amps, it is not required in this assignment. Minimum transistor width is 1.5 μ m. Minimum transistor length is 0.6 μ m. We are using an n -well CMOS process. This means that p MOS wells may be tied to any potential in the circuit (e.g., tied to V DD , tied to the source, etc.). However, the bodies of all n MOS transistors must be tied to V SS . You do not have to build a bias generator. Instead, you are allowed one (and only one) dc current source somewhere in your circuit. Note that the current from this source does count towards your total power dissipation. (Of course, you don’t have to have an ideal current source in your layout, but you do have to have the diode-connected transistor that serves as the input to the current mirror.) You may only use two dc voltage sources to power your circuit: V DD and V SS . The absolute value of each source is limited to 2.5 V, so the largest power supply you can create is ±2.5. Your power supply does not have to be symmetrical; you could use V DD = +2.0 V, V SS = -1.2 V if you wish. If you need any bias voltages (e.g., for cascode transistors), you must create a circuit to supply them; you cannot use additional dc voltage sources to supply bias voltages.
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This note was uploaded on 11/14/2011 for the course DDDD h0322 taught by Professor Whoknow during the Spring '11 term at Bina Nusantara University.

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DesignProject - ECE/CS 5720/6720 Design Project Op-Amp...

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