ECE 2140 Lab 12

ECE 2140 Lab 12 - Joshua Dean Berk Bozoklar Eric Herrera...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
Joshua Dean Berk Bozoklar, Eric Herrera Experiment 12 Intro to Verilog / Xilinx ISE Intro 03/30/2011 The George Washington University School of Engineering and Applied Science ECE 2140 Design of Logic Systems Lab Section 32 Jie Chen Intro to Verilog / Xilinx ISE Intro Abstract: This lab provides an introduction to understanding how Verilog / Xilinx work by performing a basic simulation. Introduction: The main goal of this laboratory is to start working with Xilinx [pronounce: Zy- links] ISE design suite by performing various tasks, such as creating a new project, entering the code, syntheizing the code, and simulating the codes. Methods: The lab begins by explaining the functions of a half adder. The lab then gives a code to be implemented by the verilog program: module half_adder (A, B, Sum, C_out); input A, B; output Sum, C_out; xor (Sum, A, B); and (C_out, A, B);
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
endmodule The code was copy and pasted, synthesized and simulated. The results are in the following section. Results:
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 6

ECE 2140 Lab 12 - Joshua Dean Berk Bozoklar Eric Herrera...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online