cs141-lecture12

cs141-lecture12 - Computer Science 141 Computing Hardware...

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Computer Science 141 David Brooks Computer Science 141 Computing Hardware Fall 2011 Harvard University Instructor: Prof. David Brooks dbrooks@eecs.harvard.edu
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Computer Science 141 David Brooks Annoucements Today ` s Lecture: – Intro to Computer Architecture – Busses and interfaces between CPUs, memories, I/O
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Computer Science 141 David Brooks Computer Architecture Change focus – from logic design (gate-level design) – to computer architecture (HW/SW interface of computing systems) Definitions – architecture = interface between hardware and software in a computer system – Implementation (or organization) = specific hardware design that supports interface described by architecture
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Computer Science 141 David Brooks Computer Architecture Topics – measures of performance – instruction sets – CPU, memory, and I/O design CPU cache Memory I/O devices I/O bus memory bus Single CPU Computer System Emphasis on hardware/software interactions
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Computer Science 141 David Brooks Computers built from logic gates from 0 ` s and 1 ` s to code and data for sophisticated applications Key principles of today ` s computer 1. multiple interpretations for a bit string: 0000 0001 0000 1001 0011 0000 0010 0000 two ` s complement 17 379 36010 single precision FP 1.071781159 x 10 -125 instruction add r6, r8, r9 Computer Architecture
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Computer Science 141 David Brooks Key principles of today ` s computer (cont.) 2. programs manipulated in memory, just like data: Foundation of stored-program concept and all mainstream computing! c = a + b add c, a, b add r6, r8, r9 000000 01000 01001 00110 00000 100000 compilation register allocation assembly High-Level Language Assembly Language Machine Language Binary Instruction register file register file execution
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Computer Science 141 David Brooks CPU Design in 1 Slide Fetch program instructions from memory in sequential order Decode instructions into several categories – Arithmetic/Logic Instructions • Read Two Register Values, Perform Operation, Store One Result – Memory Instructions • Load and Store Data into Memory (or on-chip caches) – Control Flow Instructions • Change the flow of instructions based on a comparison Instruction Memory Decoder ALU Data Memory Register File Program Counter
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Computer Science 141 David Brooks Top-down decomposition Understand how CPU interfaces to memory and I/O subsystems – I/O subsystem as black box too – focus on interface protocols and implementation
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This note was uploaded on 11/15/2011 for the course CS 50 taught by Professor Malan during the Spring '08 term at Harvard.

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cs141-lecture12 - Computer Science 141 Computing Hardware...

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