cs141_f11_hw4_sol

cs141_f11_hw4_sol - CS141 Assignment#4 Computer Science 141...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: CS141 Assignment #4 Computer Science 141 Weekly Assignment #4 You may hand in your solution via email ([email protected]) or in person before Wednesday’s lecture starts. 1 Problems (50 total points) Please show your work in your solutions. If you need any help, please contact the TFs with questions or meeting requests at [email protected] or post questions at Piazza. 1.(15 points) Decoder Design Memories are organized as a two-dimensional array of memory cells. The decoder selects one row from the memory by activating the row’s wordline (a wire that runs across the entire row). As we discussed during lecture(Lecture 6), designing a decoder with large fan in AND gates can be really slow. Another way to design a decoder is to split it into two sections – a predecoder that combines some of the inputs and a final stage that combines the outputs from the predecoders to select a word line. In this design, the memory size will be 64 rows and 32 columns(64x32)....
View Full Document

This note was uploaded on 11/15/2011 for the course CS 50 taught by Professor Malan during the Spring '08 term at Harvard.

Page1 / 4

cs141_f11_hw4_sol - CS141 Assignment#4 Computer Science 141...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online