FPGA Intro - 7-Bit Adder-Subtractor

FPGA Intro - 7-Bit Adder-Subtractor - 1 Digital Logic...

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1 Digital Logic Design Spring 2005 FPGA Tutorial 7 Bit Full Adder/Subtractor Objective and Introduction : An FPGA is a programmable hardware device that can be used for implementing combinational and sequential digital logic circuits. The device consists of a large structured collection of logic building blocks (for lack of better terminology) whose precise interconnection is programmable, erasable, and reprogrammable through the configuration of internal electronic “switches”. We will discuss the internal operation of programmable devices (FPGAs and CPLDs) in class near the end of the semester. The Xilinx Integrated Synthesis Environment (ISE) Tools are used to develop your design and to program the device, using a .bit file that is derived from your design (schematic layout, state diagram, or Hardware Description Language code, for example). In order to make efficient use of the logic building blocks inside the FPGA, the Xilinx ISE Tools perform complex optimization and connection routing decisions on your design before generating the appropriate bit file that is then downloaded into the device. These optimization and routing decisions are far too complex to perform by hand, making computer aided design a necessity with such devices. FPGAs provide a convenient general-purpose platform for implementing many different types of often-complex circuits using a very small amount of circuit board real estate. Although FPGAs must be programmed (a better word might be configured ), they provide a true hardware implementation running at hardware speeds. For example, the different speed grades (versions) of the XC2S50 FPGA provide basic input to output delays of approximately 4.5-5.5ns, and internal gate delays of around 1ns or less. In this example exercise, you will be revisiting the full adder you considered earlier, but with some significant additions (no pun intended!). You will design a 7-bit full adder/subtractor with ripple carry and overflow . Ripple
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2 carry is a term that is used to describe how the carry output from a 1-bit adder becomes the input to the next more significant adder in sequence. In this way the carry ripples through the circuit from least significant bit to most significant bit. There are much faster ways to perform the carry calculation, but this method is simple! Your circuit will be composed of seven 1-bit full adders, similar to your earlier design, plus some additional logic. This design can be implemented by programming the Xilinx FPGA board. You will learn how to test and verify the operation of your circuit using the National Instruments DIO-32 32- channel digital I/O system and LabView software to generate stimulus signals and observe the circuit outputs. Tutorial Exercise
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This note was uploaded on 11/16/2011 for the course ECD 251 taught by Professor Drraman during the Fall '11 term at Northwestern OSU.

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FPGA Intro - 7-Bit Adder-Subtractor - 1 Digital Logic...

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