SEMJUL08 - LECT13 - IO INTERFACING COMPLETED

SEMJUL08 - LECT13 - IO INTERFACING COMPLETED - I/O...

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I/O Interfacing ECE 511: Digital System & Microprocessor
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What we are going to learn in this session: M68230 Parallel Interface Timer. Registers in the M68230. Port initialization method. How M68230 interfaces with various devices. Delay subroutine.
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The M6230 Parallel Interface/Timer
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M68230 Parallel Interface/Timer Used by M68000 to communicate with external devices. Parallel data transfer. Has three ports: Port A, Port B, Port C. Each port is 8-bits long. Ports connect to devices. Ports need to be initialized before used. M68230 Datasheet
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M68230 Interfacing MAD Memory CS* CS* M68k M68230 Port A Port B Port C Data Bus Device #1 Device #2 Device #3 (LED, Switches, Motor, 7-Segment, Keypad, etc.)
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How M68230 connects to M68k D0-D7 D0-D7 DTACK* DTACK* R/W* R/W* CLK RESET* RESET* MAD CS* A6-A23 A1-A5 RS1-RS5 PA0-PA7 PB0-PB7 PC0-PC7 M68k M68230 CLK (Register select pins)
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M68230 Ports
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Registers in M68230 M68230 contains 23 registers. Each of the registers have a unique address that refers to them. To initialize ports, some registers need to be configured. Port General Control Register. Port X Control Register (A, B). Port X Data Direction Register (A, B, C). Port X Data Register (A, B, C).
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PGCR Port General Control Register. Used to set the operation of Port A & Port B. You only need to know (and use) Mode 0. MOVE.B #$00,PGCR
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PGCR Settings PGCR= Description $00 Unidirectional 8-bit transfer (Port A, Port B) Mode 0 $40 Unidirectional 16-bit transfer (Port A + Port B) 1 $80 Bidirectional 8-bit transfer on Port B, bit I/O on Port A. 2 $C0 Bidirectional 16-bit transfer (Port A + Port B) 3
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Port X Control Register Used to set buffering of input/output on PXDR. Three modes: Mode 00. Mode 01. Mode 1X. You only need to know (and use) mode 1X.
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PXCR Settings PXCR= Description $00 Double-buffered input Sub-mode 00 $40 Double-buffered output 01 $80 Bit I/O 1X
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Port X Data Direction Register Used to specify the direction of data transfer for each bit in the port. Two states: If PXDDR bit = 0, will be set as input. If PXDDR bit = 1, will be set as output.
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Port X Data Register Contains the data sent/received to/from devices. Each PXDR carries 8-bits of data. There are three data registers in the M68230: PADR, PBDR, PCDR.
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Port Initialization To perform port initialization: Assign the register addresses to a unique name. PGCR must be set to #$00. PXCR must be set to #$80. Set PXDDR to input or output.
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Port Initialization Example START ORG $XXXXXX PGCR EQU $A00001 PACR EQU $A0000D PBCR EQU $A0000F PADDR EQU $A00005 PBDDR EQU $A00007 PCDDR EQU $A00009 PADR EQU $A00011 PBDR EQU $A00013 PCDR EQU $A00019 MOVE.B #$00,PGCR MOVE.B #$80,PACR/PBCR MOVE.B #$XX,PADDR/PBDDR/PCDDR (DEPENDING ON THE H/W) Port Address PGCR $A00001 PACR $A0000D PBCR $A0000F PADDR $A00005 PBDDR $A00007 PCDDR $A00009 PADR $A00011 PBDR $A00013 PCDR $A00019
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68230 Interfacing
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M68230 Interfacing M68230 interfacing is similar to memory interfacing in last chapter.
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SEMJUL08 - LECT13 - IO INTERFACING COMPLETED - I/O...

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