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Unformatted text preview: 184 Class 9: Op Amps II: Departures from Ideal Topics:
0 old:
— passive versions of circuits now built with op amps: integrator,
differentiator, rectiﬁer '
.0 new: — three more important circuits (applications): 9 integrator
O differentiator O rectiﬁer
— op amp departures from ideal
Q offset voltage
‘9 bias current
offset current
9 frequencylimitations: openloop gain; slew rate
9 output Current limit ' Today we end our honeymoon with the op amp: we admit it is not ideal. But we continue
to admire it: we look at more applications, and as we do, we continue to rely on our ﬁrst,
simplest view of op amp circuits, the view summarized in the'Golden Rules. After using the Golden Rules to make sense of these circuits, we begin to qualify those
rules, recognizing, for example, that op amp inputs draw a little current. Let’s start with
three important new applications; then we’ll move to the gloomier topic of op amp
imperfections. 185 N9 — 2 Class 9: Op Amps 11: Departures from Ideal 1. Three More Applications: Integrator, Differentiator, Rectiﬁer Integrator
To appreciate how very good an op amp integrator can be, we should recall the defects of thesimple RC “integrator” you met in Chapter 1. Passive RC integrator Text sec. 1.15
Lab 23 R .
V‘n Vour I'D I I I In ‘ i
l I ".th C .
I out M ouE/\ Figure N91: RC “integrator:" integrates, sortof, if you feed it the right frequency
To make the RC behave like an integrator, we had to make sure that Text sec. J.J5,p. 27
Vout « Vin . This kept us on the nearly—straight section of the curving exponentialcharging curve, when
we put a square wave in. The circuit failed to the extent that Vout moved away from ground. But the output had to move away from ground, in order to give an output signal. 017 amp version
Text sec. 4.19;
Lab 9—2
The op amp integrator solves the problem elegantly, by letting us tie the cap’s charging
point to 0 volts, while allowing us to get a signal out. “Virtual ground” lets us have it both ways. C Figure N92: Op amp integrator: virtual ground is just what we needed The op amp integrator is so good that one needs to prevent its output from sailing off to
saturation (that is, to one of the supplies) as it integrates error signals: over time, a tiny lack
of symmetry in the input waveform will accumulate; so will tiny op amp errors. 186 ' Class 9: Op Amps 11: Departures from Ideal i N9 — 3 So, practical op amp integrators include some scheme to prevent the cap’s charging to
saturation: at) One remedy: a large resistor in parallel with the cap (this leaks off a small current,‘
undoing the effect of a small error current in); Text . 223
p look took b Figure N93: Integrator saved from saturation by resistor parallel Cfccdback 10H took Eﬁects 0f the resistor Evidently, the resistor compromises performance of the integrator. But we can ﬁgure out
by how much. There are several alternative ways to describe its effects: The resistor limits DC gain ,
In the circuit above, where Rin = 100k and Rmdback = 10M,
the DC gain is —100. So a DC input error of :1 mV —>
output errorof =100mV. The integrator still works ﬁne,
apart 'from this error. ~ Theresistor allows a predictable DC leakage
Suppose we apply a DC input of IV for a while; when the
output reaches —1V, the error current is 1/100 the input or
“signal” current (because Rfecdback = 100°Rin). This error
grows if Vout grows relative to in. ' The resistor does no appreciable harm above some low frequency
As fin .riSes from zero, XC shrinks, and at some low
frequency XC becomes less than R. Soon R is utterly
insigniﬁcant. »
Xc = R, as you know, at f = l/ZarRC. For the components
shown in the circuit above—Rfcedback=10M, C=luF——that
frequency is about 0.01Hz! _ ' m—ehannet
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on I) N9 — 4 Class 9: Op Amps II: Departures from Ideal 187 A detail: how the resistor T works
Here’s a diagram'to persuade you that the clever Tresistor arrangement does indeed make the 100k resistor look about 100X as large:
Igedbuk {s #723 what it
“mull have been Wl+]’1 R1 None)
=> 7?}; (eFFedin/e] z 100x El Vlr'i‘u i R I R
9””“3 iodk / 10<1>k 1k Vane ‘ I“
R2
7 took _
1k Figure N9.4: How the T arrangement enlarges apparent R values
Neat? The scheme is useful because the lower RThevenm of the T feedbaCk network has two
good effects: — it generates smaller [bias errors than the use of giant resistors would (we’ll discuss
this problem, below); , — it drives stray capacitance at the op amp input better (avoiding unintentional low
pass effectsin the feedback); this is not important here, but is in a circuit where no ' capacitor sits parallel to a big feedback resistor. b) Another remedy: a switch in parallel with the cap (this has to be closed brieﬂy, from time to time).
+10 reset
0 reset o——[ L
—m—l 1— n—channei
HOSFET (ouin bad ﬁrmnnalj' or Has anal
Swi'i‘ch 03  Figure N95: Integrator saved from saturation by discharge switch
The switch produces a more perfect integrator, but is more of a nuisance to drive. 188 Class 9: Op Amps 11; Departures from Ideal N9 — 5 Differentiator Text sec. 4.20;
Lab 93 Again the contrast with a passive differentiator helps one appreciate the op amp version: a . r ,
v,,,(e)——l We) IN M m
’2‘ , m m _ reveals RC shape
Figure N96: RC “differentiator:" differentiates, sortof, if RC kept very small To make it work, we must make sure that
Tatsec. 1.14, 17.25. dVout/Clt << dVin/dt Again the op amp version exploits virtual ground to remove that restriction: T ext sec. 4.20,
pp. 11425,
ﬁgs. 4.51, 4.52 $ " ‘ 73%" bases in ... R I 3 dﬂnnfzadfr A. .wﬁl;_
; migrain
c I ‘ (—c/a/aa'aie)
l E. 7 Figure N9.7: Op amp differentiator: simple (idealized); practical
This op amp differentiator is a little disappointing, however: it must be compromised in
order to work at all. A practical differentiator, shown on the right in the ﬁgure above, turns
into an integrator (of all things!) at some high frequency. _
This scheme is necessary to prevent oscillations (we will look more closely at this topic a
class or two hence). Active Rectiﬁer T ext sec. 4.10,
pp. 18788, ﬁgs. 4.25, 4.26;
Lab 94 The simple passive rectiﬁer of Chapter 1 was blind to inputsv< about 0.6 v, and put an.
offset of that amount between input and output. The Op amp version hides the diode drop: T s/eu—nfe—llrh/fed
IN afpr‘aac}. +0
Sa+ura+fm d . /—~“‘;¥F 0'6 5 slew—refe(mh‘eii
OUT recon/e 7%":
xxx, sa+ura on Figure N9.8: Passive and active rectiﬁers N9 — 6 Class 9: Op Amps 11: Departures from Ideal . 189 I The circuit shown saturates for one input condition. That is poor: produces an output glitch
1 ‘ (caused by delay) as it comes up out of saturation. In the lab you will build an improved active rectiﬁer that cleverly stays out of saturation (how does it work?) Fig.4.27; t Lab9—5 f i g 1 b—qum’s always ‘Feadhaeks
50, never sa'tur‘ale Figure N93: Improved active rectiﬁer 2. 0}) Amp Departures from Ideal
Let’s admit it: op amps aren‘t quite as good as we have been telling you: the Golden Rules exaggerate a bit: ' the inputs do draw (or squirt) a little current;
0 the inputs are not held at precisely equal voltages. 3Here are three circuits that always deliver a saturated output after a short time. They
, would not if op amps and all components were ideal: I ﬁgure N9.10: Three circuits sure to saturate. why? I Op Amp Errors Text sec. 4.11, 4.12;
Lab 9] . . Wevwill treat, in turn, the following op amp errors: voltage oﬁfset:
bias current offset current
frequency limitations: openloop gain rolloff,‘ slew rate output current limit. Offset Voltage ; Textsec,4.1], p. 192;
i 4.12.12.1‘94 Offset Voltage: 1705 “The difference in input voltage necessary to bring the output to
zero...” (Text, p. 192) I 190 Class 9: Op Amps 11: Departures from Ideal' N9 — 7 This spec describes the amp’s delusion that it is. seeing a voltage difference between its
inputs when it is not. The amp makes this mistake because of imperfect matching between the two sides of its differential input stage. um— . '
ml!!! Um“
Magma” Rs=wm=zsvc IEﬂﬂ '
Figure N9.11: 411 Spec: Vonm . You can compensate for this mismatch by .deliberately pulling more current out of one
side of the input stage than out of the other, to balance things again. This correction is
called ‘trirnming offset,’ and you will do it in today’s lab. But this trimming is a nuisance,
and the balancing does not last: time and temperaturechange throw Voffset off again. The better remedies are, instead— LF41 A 0 use a good op amp, with low Voffset;
0 design the circuit to work well with the Voﬁset of the amp you have chosen. / 3521mm ofAHP: 3979‘: and anr... posh/1v is conch! Ekiﬁ‘A“
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L . _ _ . . . _ #5. Vi, . . _ . _ _ .. 10k \ﬁ—Im ,M by llkn'nj rain}; of MFR—Shae Jrain eu'rrznts Figure N912: Inside the 411: schematics: simpliﬁed, and detailed N9 — 8 . Class 9: Op Amps II: Departures from Ideal _ 191 Bias Current
Text sec. 4.11, p. 190; sec.4.12,p.194 . t V +5 amﬂm
as 0 rren s=l v Im_n_A
“P” m— EEI£
lhput Bias Curreht vs= ixsv mII 5‘1 Figure N9.13: 411 Specs: 11,,” and 1m, Bias Current: I “as
Ibias is a DC current ﬂowing in or out at the input terminals (it is deﬁned
as the average of the currents at the two terminals). For an ampliﬁer with. bipolar transistors at the input stage, [bias is base current; for a FET
input op amp like the 411, Ibias is a leakage current: it is tiny, therefore, but also grows i rapidly with temperature:
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0.001
50°c o"c 50°C 1ad’c
temper?va 'V ; Figure N9.14: 411 bias current: tiny, but grows fast with temperature The bias current ﬂows through the resistive path feeding each input; it can, therefore, 7
generate an "input error voltage, which may be ampliﬁed highly to generate an appreciable
output error: the Lab exercise uses a high~gain DC ampliﬁer for just that purpose: % Figure N9.15_: Lab circuit: uses highgain dc amp to make errors measurable “ v But notice that the lab notes ask you to use a 741 op amp, not a 411, to make the errors
{ substantial. That requirement suggests that often you will not need to worry about the
effects of bias current: true, but you should know how to judge whether or not to worry. To minimize the effects of. bias current, match the resistances of the paths that feed the
two op amp inputs. Here are examples of circuits that do or do not balance paths: ' in 192 ' Class 9: Op Amps 11: Departures from Ideal N9 — 9' —‘ i
100.0.
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100k 100k
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£4 balancgd L model {Dr balarKinj Invert‘fnj my Figure N9.16: Balanced Resistive paths output errors resultinG from bias current Once you have balanced these resistive paths, [bias no longer causes output errors. But a
difference between currents at the inputs still does. That difference is called— Offset Current Text sec. 4.11, p. 190;
sec. 4.12, p. 195 Offset Current: 1017:“, The difference between the bias currents ﬂowing at the two inputs. For the 411 the [OS speciﬁcation is about 1/2 IbiaS; for the bipolar op amps [OS is smaller
relative to 15m. But recall how tiny Ibias is for the 41 1 and other FET—input devices. As noted just above, even when the resistances seen by the two inputs are balanced, an error will occur because of this diﬁ‘erence in currents. Remedy? Use resistances of
moderate value. (< a few 10’s of Megohrns; recall the argument for the clever T resistor trick noted above.)
Note, by the way, that even if bias current were zero, still you would need to provide a DC connection to each op amp input, to deﬁne the voltage there; otherwise stray capacitance
gradually would charge with leakage currents (in the PC board, if nowhere. else). So, these two circuits are bad: Figure N9.17: One must provide a DC connection to each op amp input N9 — 10 Class 9: Op Amps II: Departures from Ideal 193~ Measuring and correcting eﬁects 0f Voﬁse, and I bias, in lab exercise 91
The lab notes suggest that you go through this process in .a particular sequence. Make
sure you understand why you are asked to proceed as stated there: . You start with a highgain amp (x1000) that will show large output errors for small inpu
errors. At the outset, the effects of Voffset and Ibias are commingled. You cannot tell, looking
at the output, what the effect of either error is, taken by itself. Their effects may even tend to cancel. in out 10k :— took at 4":le (as here) owlput Shows execis of Several errorsJ Summed ——
T especially 1], , V55 100.11 ' Figure N9.18: Lab 91I’s highgain DC amp, once more
The procedure suggested goes this way: . o arrange things so that the effects. of [bias are negligible. (How?) — Measure the output error; infer the input error, and thus V05.
—— Trim V05 to aminimum. 0 arrange things so that [bias causes an input error. — measure the output error so caused, and infer the input error, and thus IN”.
— Alter the circuit so as to minimize the error caused by Ibias ' 0 Infer IDS from the remaining output error. Make sense? AC Ampliﬁer: An elegant way to minimize eﬁects offblas, X03 and 105 Text sec. 4.05,
p. 179, ﬁg.4.7;
Lab 101 If you need to amplify AC signals only,,you can make the output errors caused by V03,
I bias and [OS negligible in a clever way: just cut the DC gain to unity: R:
6., — 1+ ENE: roughb, gain is damn 3&3 R. Rik when :_ = XI 2k 18 c (My 1?, rd = 5R1)
WEI ' Figure N919: AC ampliﬁer: neatly makes effects of small errors at input small atpoutput
What’s its f3dB? If one ignores the “l” in the gain expression, output amplitude is down
3dB when the denominator in the gain expression is ‘12(R1). But that happens when Xc =
R1, and that happens, as you well know, at f3dB= 1 / (ZanC). 194 “ Class 9: Op Amps II: Departures from Ideal N9  11 This is the same notion you used to choose the emitterbypassing capacitor, back in
Chapter 2: '  ' Text sec. 213, p.85 Re
reﬁgc ca:— gain is damn 343
wﬁen XC = r5 / Figure N9.20: Gain is down 3dB when denominator (series impedance of R and C) is up to Rw/Z: true for bypassed—emitter
amp, and for opamp AC amp Slew Rate & Rolloff of Gain Text sec. 4.11, pp. 19192;
sec. 4.12, p. 193 These effects turn out to be caused, deliberately, by 'a gainkilling capacitor planted
within the op amp. We will talk about this compensation device next time, when we
consider op amp stability. For the moment, we will note that the 0p amp’s gain falls off at
—6dB/dctave (as if the output had been passed through a simple RC lowpass: in effect, it
has been!); so the chip’s very high gain, necessary to make feedback fruitful, evaporates
steadily with increasing frequency—and is gone at a few MHz (about 4 MHz for the 411). 100
A so
an
3
a“. as Vs: 135V /
Avon. Larﬂe‘s‘ﬂ'ﬁl Vo =1IDV 25 Zoo V/mV
VoH’aSe 3m PL=7J< ﬁ=K°C »
In Figure N921: 411 gain roll—off: spec and curves These speciﬁcations deﬁne an upper limit on the usefulness of all op amp circuits; that limit explains Why not every circuit should be built with op amps, wonderful though the
effects of feedback are. o.
1' 10 too 1k 10k'1aok m 10:4 72:23 ache], Hz N9 —112 Class 9: Op Amps II: Departures from Ideal 195 . i Output Current Limit 4 Text sec. 4.11, p. 191;
sec. 4.12,p. I94 This is a selfprotection trick inserted into the output stage, to protect the small transistors 1] there from the heating that otherwise would result when some clumsy user overloaded the , amp. You saw a curve like this one in the ﬁrst op amp lab: r l 30 so
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{ ‘ ([93 scale) (Unear scale) Figure ‘N9.22: Output current limit: output clips under load, despite very low Ra,“ 196 Ch.4: Worked Examples: Integrators; Imperfect op amps Two worked examples: 1. Integrator design
2. Calculating effect on integrator of op amp errors 1. Integrator Design: Problem: Integrator
Design an op amp integrator that will ramp at + lV/ms given a + 1V DC input. Include protection against drift to saturation, and let the input
impedance be 2 10MQ. Solution V Let’s start with a sketch, postponing the choice of part values. The Sign of the output
ramp, and the high required input impedance require a couple of extra op amps; but we
don’t mind: remember?: op amps are cheap. 'gﬂoosrs T T k cA/vcELs
CI Reorr’s R w . Ill/VERSION
’ Figure X9.1: Integrator: skeleton circuit The resistor in the feedback path will limit the DC gain, keeping the op amp output from
sailing away to saturation. ’ A subtle point: why not balance paths for [bias We seem to be violating our own design rules by failing to provide a resistor to ground on
the noninverting side of the integrator. Here’s the argument that says it turns out better not
to do such balancing in this context: 0 we would use a lowbias‘current op amp in an integrator; probably we would use
an op amp with FET input and the pA currents that are usual for this type; This
kind of op amp’s 103 will be only about a factor of two better (lower) than its Ibias. 0 why not take that factor of two, though? Because a side effect of the large R on the
non—inverting terminal is increased vulnerability to noise there. In the present case,
we would use 100k at that point, whereas now the noninverting terminal is driven by a good low impedance (groundl). Now for part values: we want DC gain of around 100, so we don’t want R1 huge: make it,
say, 100k; then waback can be about 10M. 1 \ X9 — 2 Ch.4: Worked Examples: Integrators; Imperfect op amps 197 Given R1, we can solve for the required C using our usual description of a capacitor’s
behavior, _I_ 5 Q JV/dt. I is the current that ﬂows when the 1V input is applied; dV/dt was given us as a design’ goal. We can solve for C: ' 40M \‘5 C=I . I
@‘r ’ 2' _
LET 7?,= 700K. THE/V I: 0.0.1,".‘A @ \/lA/=4V __ _ 0.!)th =
’> C“ 10 V/s‘ 0‘01”: Figure X92: Integrator with part values speciﬁed 2. 0p Amp Errors: effects on an integrator  An integrator will show the effects of even small DC errors, over time. In the next
example we will try to calculate the size of those output errors. » Problem: E ﬂeet an integrator of op amp errors
What output drift rate would you see in the circuit below, assuming that
you use each of the listed op amps. The circuit input is grounded. 4M®4M Figure X93 : Integrator: what drift rates? Proposed remedy: resistor “1" feedback network 0P amp type Vos Ihias
741C 6mV SOOIIA
OP—07A 25w 2nA
LF41 1 2mV 0.2nA What happens if we add the indicated resistor network parallel to the
feedback capacitor? 198 Ch.4: Worked Examples: Integrators; Imperfect op amps , X9 — 3 Solution: The oﬁ‘set voltage, V03, causes the op amp to pull its inverting terminal (by means of the .
feedback network, of course) not exactly to ground, but to a voltage V05 away from ground
(we cannot predict the sign of this error). That error causes current to ﬂow in the resistor; that current can’t go into the op amp, so it ﬂows into the capacitor. The bias current ﬂows into (or out of) the op amp’s inverting terminal. This produces a
drop across the input resistor, which must be canceled by an equal value of current ﬂowing
through the integrating capacitor(that is, it produces an output voltage ramp). Worst case, these two currents ﬂowing in the capacitor simply add. So, we get the
following results: ‘ Op amp type VOS Thins I <— V05 Sum of 1’s dv/dt '
741C 6mV SOOnA 6nA == SOOnA 50V/s
(SOmV/ms)
OP_07A 25uV ZnA 25pA = 2nA 0.2 V/s
LF411 2mV 0.2nA 2nA 2.2nA 0.2 V/s Figure X9.4: Output errors 'for a particular integrator made with each of three op amps Question: “What happens if we add the indicated resistor network parallel to the feedback
capacitor?”  Answer: The Resistor network. .. Text sec. 4.19,
ﬁg. 4.49, p. 223 The network looks like about _100M§2: one part in 100 of Vout reaches point ‘X;’ so, the
current ﬂowing through the leftmost resistor is about 1/100 what it would be if that resistor alone (1M) were in the feedback path. In other words, if we apply Ohm’s Law —R(appmnt)
/I—— we 'ﬁnd that the network behaves like a resistor'of about 100M (101M, if = Vout—opamp
you care). . . Its Eﬁect The ‘lOOMQ’ resistor gives the circuit a DC gain of «100. So, instead of sailing off to
saturation, the op amp output will begin to drift at about the rate determined in the earlier
section of this problem—and then will slow and ﬁnally level off at —100><(input error
voltage). ' . ’ The input error voltage is the sum of V03 and Ibias ﬂowing in the resistance it “sees.”
What is that? It’s the 1M input resistor parallel the other path, which looks like 1M + 10K
= 1M. Parallel, the two look like 0.5MQ: Verror(in) = (1 bias X RThbias) + Vos
, This input error (of undetermined sign) gets ampliﬁed by —100. Here are the speciﬁc results
for the three op amps. Op amp type V05 Ibias V <— Ibias , Sum Output Error
(IbiasijMQ) __—__—___—.__._'—___.—————————————'——— 741C 6mV SOOnA 0.25V = —0.25V +25V (saturation) OP—07A ZSLLV 211A lmV = lmV :thOmV LF411 ZmV 0.2nA 0.1mV 2.1mV = .200mV Figure X95: Output error (DC) for integrator with feedback resistance added .. ﬂ X9 — 4 Ch.4: Worked Examples: Integrators; Imperfect op amps 199 And here is a sketch of what the output voltage error would look like if we started with no
charge on the cap: disaster for the ‘741, but tolerable results for both of the better op amps: —7LH If n naf
Predz‘d‘db/c
for OP07
or “+11 Figure X9.6: Feedback resistor limits integrator’s output drift: effect quantiﬁed _______________—————+——————— ...
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This note was uploaded on 11/15/2011 for the course PHYS 2300 taught by Professor Staff during the Summer '09 term at Auburn University.
 Summer '09
 Staff
 Physics, Electronics

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