2003-Computer_Architecture-solutions

# 2003-Computer_Architecture-solutions - Computer Science...

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Computer Science Comprehensive Examination Computer Architecture [100 points] This examination is open book. Please do all of your work on these sheets. Do not do your work in a blue book. Number: __________________________________________________ Problem Max Score Your Score 1 33 2 33 3 34 TOTAL 100

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Problem 1: Memory Systems [33 Points 4 points each + 1 free] A. Compared to a 16K direct-mapped cache, what type of misses will a 16K fully associative cache have fewer of? Circle all that apply. (a) compulsory (b) conflict (c) capacity (b) conflict misses B. Suppose that cache A, a 16K-byte four-way set associative cache, cache B, a 16K-byte direct-mapped cache, and cache C, a 4K-byte direct-mapped cache are all referenced with an identical address sequence. All caches use a true least-recently used (LRU) replacement policy. Which of the following statements are true: (circle all that apply) (a) A will contain a superset of the data in B (b) A will contain a superset of the data in C (c) B will contain a superset of the data in A (d) B will contain a superset of the data in C (b) A contains a superset of C. Cache C is equivalent to one “way” of A . and (d) B contains a superset of C since both are direct mapped and B is larger. C. In a 64K-byte four-way set-associative cache with 128-byte blocks, how large is the index field used to address the cache array? (write down the number of bits) __ 7 _________________ D. If the cache of question 1.C is physically tagged and physical addresses are 40-bits long, what is the minimum possible length the tag may be for correct operation? (write down the number of bits) ___ 26 = 40-7 (index) – 7 (block) ________________ E. A processors needs to support multiple processes running simultaneously with complete isolation (each process cannot access the memory of any other process). What is the minimum set of features in the architecture required to implement this complete isolation? (Circle minimal subset) (a) Atomic branch and entry to privileged mode (in which all of memory can be addressed) (b) A single base and length (segment) register (c) Multiple base and length (segment) registers, one per process (d) A translation look-aside buffer with a trap to a privileged mode handler routine on miss. (a) and (b) suffice, as does (d) by itself (either gets full credit)
F. Replacing a single memory bank with multiple interleaved memory banks has which of the following effects? (circle all that apply) (a) Increases latency (b) Increases bandwidth (c) Increases reliability (d) Decreases latency (b) G. A bus-based cache coherence protocol “snoops” the directory of each processor’s level-2 cache on each bus access. For this scheme to work, what relationship between the level-1 cache and level-2 cache must be maintained? (one word) inclusion H. A cache coherent multiprocessor has four processors, each with a 16Mbyte direct-mapped level-2 cache that is organized into 128-byte lines. Each processor makes single-word (8 byte) references

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## This note was uploaded on 11/18/2011 for the course EE 282 at Stanford.

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2003-Computer_Architecture-solutions - Computer Science...

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