2004-Computer_Architecture-solutions

2004-Computer_Architecture-solutions - Computer Science...

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Computer Science Comprehensive Examination Computer Architecture [60 points] This examination is open book. Please do all of your work on these sheets. Do not do your work in a blue book. Number: __________________________________________________ Problem Max Score Your Score 1 20 2 20 3 20 TOTAL 60 Autumn 2004 Page 1 Architecture Comp
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Problem 1: Short Answer [20 points] A. [7 points] Assume a pipelined processor with N pipeline stages. As we increase N, briefly explain that happens to the following (increase/decrease + 1 sentence reasoning) - Clock cycle time: Decreases – fewer gates per pipeline stage - Cycles per instructions: Increases – more data and control hazards Considering clock cycle time only, is there a limit or point of diminishing returns for the number of pipeline stages in a processor? Why? Yes there is. Clock cycle is limited by clock skew and pipeline register clocking overhead. As we subdivide the work for each instruction in more pipeline stages, eventually the clock cycle will become equal to the skew+overhead. Deeper pipelining, will not lead to additional clock cycle benefits . [7 points] Assume a first level data cache with capacity (C), associativity (A), and block size (B). Draw the expected effect on hit rate as C, A, and B increase respectively. In each case, we vary one of the three parameters, while the other two are kept constant. Mark any interesting points on the graphs with 3-4 words to provide some reasoning. . Conflict misses eliminated C=working set Hit rate C A Prefetching due to spatial locality No enough blocks B Autumn 2004 Page 2 Architecture Comp
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B. [6 points] What does the following MIPS code do? What is the instruction cache miss rate? What is the data cache miss rate? Assume the caches are initially empty and have a 16 byte line size. move $t0, $a0 addi $t1, $t0, 4000 loop: Sw $t0, 0($t0) addi $t0, $t0, 4 slt $t2, $t0, $t1 bne $t2, $zero, loop exit: The code intitializes a 1000 words to the memory address of the word Icache miss rate = 2/(2 + 1000*4) = 2/4002 = 0.05% Dcache miss rate = 1/4 = 25% Autumn 2004 Page 3 Architecture Comp
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Problem 2: Instruction-Set Architecture Design [20 Points] Your task is to redesign the way branches work in the MIPS ISA to create a new architecture called MIPS-new. You decide to add branches with arbitrary compares which are called complex branches. You are given the following information about
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2004-Computer_Architecture-solutions - Computer Science...

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