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Unformatted text preview: EE108B Spring 2003-2004 Prof. Kozyrakis Homework #3 Due Thursday, May 13, 5 PM in Gates 310 Work in groups of 3 students, but turn in only one HW per group. 1. (15 points) Consider the following snippet of code: lw $2, 0($1) ori $2, $2, 0xffff lw $3, 4($1) addu $4, $2, $3 lw $5, 0($4) lw $6, 8($1) subu $7, $5, $6 sw $7, 0($4) a. (5 points) Identify all the dependencies present in this code and classify then based on the type of dependency, such as RAW, WAW or WAR? b. (2 points) Identify the instructions that will require interlocks (pipeline stalls) if the above sequence is executed on a 5-stage pipelined MIPS processor without forwarding logic. In total, how many cycles of interlocks are required? NOTE: We will be following the convention that an instruction is stalled in the stage before the hazard will occur. To illustrate this using the example in the text book, pg 493-494, the and depends on the output of the lw . This implies that the hazard a MEM/EX hazard, so the and instruction is stalled in the Decode stage. c. (5 points) Fill in the pipeline diagram below for the execution of the above code sequence for a 5-stage pipeline with full forwarding logic. Please use acronyms F, D, X, M and W for the 5 pipeline stages. Please mark stalls with -- and all cases of forwarding with arrows to connect the source and destination stages....
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This note was uploaded on 11/18/2011 for the course EE 108A taught by Professor Dally during the Spring '04 term at Stanford.
- Spring '04