hw4 - EE108B Spring 2003-2004 Prof. Kozyrakis Homework #4...

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EE108B Spring 2003-2004 Prof. Kozyrakis Homework #4 Due Thursday, May 20, 5 PM in Gates 310 Work in groups of 3 students, but turn in only one HW per group. 1. (Total 10 points) You are building a system around a processor that runs at 2.1 GHz and has a CPI of 0.8 excluding memory accesses. The only instructions that read or write from memory are loads (20% of all instructions) and stores (10% of all instructions). The memory system for this computer is composed of a split L1 cache that imposes no penalty on hits. Both the Instruction Cache (I-cache) and Data cache (D-cache) are direct mapped and hold 32 KB each. The I-cache has a 3% miss rate and the 32-byte blocks and the D-cache is write through with a 7 % miss rate and 16 byte blocks. There is a perfect write buffer (i.e. eliminates stalls for 100% of writes) on the D-cache. The 512 KB write-back, unified L2 cache has 64-byte blocks and has an access time 20 ns. Off all memory references sent to the L2 cache in this system, 70% are satisfied without going to main memory. In addition, 60% of all blocks are dirty. The main memory has an access latency of 55 ns. Note: All data is stored in main memory (there is no need for a disk). The caches are write-allocate, fetch on miss. Access time is the time between when a read is requested and when the first word arrives. Give answers in nanoseconds (ns).
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This note was uploaded on 11/18/2011 for the course EE 108A taught by Professor Dally during the Spring '04 term at Stanford.

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hw4 - EE108B Spring 2003-2004 Prof. Kozyrakis Homework #4...

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