hw4 - EE108B Winter 2003-2004 Handout #29 Homework #4 Due...

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EE108B Winter 2003-2004 Handout #29 Homework #4 Due Thurs Feb 26, 5 PM in Gates 408 1. (Total 10 points) You are building a system around a processor that runs at 1.1 GHz and has a CPI of 0.7, which excludes loading from and saving to memory. The only instructions that read or write from memory are loads (20% of all instructions) and stores (5% of all instructions). The memory system for this computer is composed of a split L1 cache that imposes no penalty on hits. Both the Instruction Cache (I-cache) and Data cache (D-cache) are direct mapped and hold 32 KB each. The I-cache has a 2% miss rate and the 32-byte blocks and the D-cache is write through with a 5 % miss rate and 16 byte blocks. There is a perfect write buffer that allows single cycle writes and eliminates all stalls from the write-through D-cache. The 512 KB write-back, unified L2 cache has 64-byte blocks. It takes 15 ns to refill a L1 cache line from the L2 cache. Of all memory references sent to the L2 cache in this system, 80% are satisfied without going to main memory. In addition, 50% of all blocks are dirty. The main memory takes 60 ns to refill a L2 cache line. Note: i. All data is stored in main memory (there is no need for a disk). ii. The caches are write-allocate, fetch on miss. iii. There is no write buffer for L2 dirty lines. iv. Give answers in nanoseconds (ns). a. What is the AMAT for instruction accesses? b. What is the AMAT for data reads? c. What is the AMAT for data writes? d. What is the overall CPI, which includes memory access? (hint: make use of answers from parts a-c) e. What is the CPU time? Assume a typical program executes 1.5 million instructions. 2. (Total 20 points) Ben Bitdiddle has just purchased a brand-new machine and is curious as to what its cache architecture is (direct mapped vs. set-associative, how large is the cache, etc.) Being a graduate of EE182, Ben decides to write a short program to test the behavior of his L1 cache. Ben knows the following about his machine, from the manufacturer’s literature: 1
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EE108B Winter 2003-2004 Handout #29 i. Cache block is at least 4 bytes (but Ben doesn’t know the size of a cache block) ii. Total size of L1 (in bytes) is a power of two
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hw4 - EE108B Winter 2003-2004 Handout #29 Homework #4 Due...

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