hw5 - EE108B Winter 2003-2004 Handout #29 Homework #5 Due...

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Winter 2003-2004 Handout #29 Homework #5 Due Tues Mar 9, 5 PM in Gates 408 1. (5 points) memory, and the same am[5 points] The following simplified diagram shows two potential ways of numbering the sectors of data on a disk (only two tracks are shown and each track has eight sectors). Assuming that typical reads are contiguous (e.g., all 16 sectors are read in order), which way of numbering the sectors will be likely to result in higher performance? Why? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 14 15 8 9 10 11 12 13 2. (Total 25 points) Some buses, such as the PCI bus used in modern desktops, use multiplexed address/data lines. The multiplexing of this information leads to an interesting tradeoff between bandwidth and latency. Since PCI is complicated, consider the following simple transaction: 2 cycles 1 cycle 1cycle 1 cycle Address phase Data Data Data a. D Assuming a 33 MHz bus and a 32 bit address/data bus, what is the theoretical maximum bandwidth of this bus in MB/s? b. The arbitration scheme used on the bus is called “round robin” whereby each of the devices can have access to the bus one at a time. So, if there are three devices on the bus then device A is given access to the bus first, then device B, and finally device C. When it is finished, device A is given the bus again. Given this scheme, what is the worst-case latency of this bus (i.e. how long would A have to wait before it could become the bus master?) c. Derive an equation for the peak bandwidth as a function of the transaction timer value. d. Derive an equation for the maximum latency as a function of the transaction timer value. 1
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This note was uploaded on 11/18/2011 for the course EE 108A taught by Professor Dally during the Winter '04 term at Stanford.

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hw5 - EE108B Winter 2003-2004 Handout #29 Homework #5 Due...

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