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hw5_sol

# hw5_sol - EE108B Winter 2003-2004 Handout Homework#5(Total...

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EE108B Winter 2003-2004 Handout #? Assuming a 33 MHz bus and a 32 bit address/data bus, what is the theoretical maximum bandwidth of this bus in MB/s? Answer: The bus can transfer 32 bits on each clock edge at a clock rate of 33 MHz, so the theoretical maximum bandwidth is 32 bits * 33 MHz = 132 MB/s. b. (2 points) The arbitration scheme used on the bus is called “round robin”, whereby each of the devices can have access to the bus one at a time. So, if there are three devices on the bus, then device A is given access to the bus first, then device B, and finally device C. When it is finished, device A is given the bus again. Given this scheme, what is the worst-case latency of this bus i.e. how long would A have to wait before it could become the bus master? Answer: Since the data phase can be of any length, there is no requirement that A relinquish the bus and therefore the worst-case delay for A to become the bus master again is infinite. c. (5 points) Derive an equation for the peak bandwidth as a function of the transaction timer value.
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hw5_sol - EE108B Winter 2003-2004 Handout Homework#5(Total...

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