hw5_sol - EE108B Winter 2003-2004 Handout #? Homework #5...

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EE108B Winter 2003-2004 Handout #? Homework #5 (Total 105 points) Due Tues Mar 9, 5 PM in Gates 408 1. (5 points) The following simplified diagram shows two potential ways of numbering the sectors of data on a disk (only two tracks are shown and each track has eight sectors). Assuming that typical reads are contiguous e.g. all 16 sectors are read in order, which way of numbering the sectors will be likely to result in higher performance? Why? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 14 15 8 9 10 11 12 13 Answer: The method on the right will yield the best performance (1 point) . The disk drive head begins reading at sector 0 and as the platter rotates, the head continues reading through the end of sector 7. After reading sector 7, a seek is necessary to position the head over the track containing sector 8 (1 point) . While the head is seeking, the platter will continue rotating (1 point) . Therefore, in the organization on the left, the platter will have rotated so that the head is past the start of sector 8 by the time the seek is finished (1 point) . A nearly full rotation will then be required to read sector 8. The organization on the right avoids this problem by staggering the sectors so that the seek can be completed before the head has rotated over sector 8 (1 point) . The UNIX Fast File System uses a similar idea in selecting “rotationally-optimum” sectors when placing files on disk. 2. (Total 25 points) Some buses, such as the PCI bus used in modern desktops, use multiplexed address/data lines. The multiplexing of this information leads to an interesting tradeoff between bandwidth and latency. Since PCI is complicated, consider the following simple transaction: 2 cycles 1 cycle 1cycle 1 cycle Address phase Data Data Data a. (2 points) 1
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EE108B Winter 2003-2004 Handout #? Assuming a 33 MHz bus and a 32 bit address/data bus, what is the theoretical maximum bandwidth of this bus in MB/s? Answer: The bus can transfer 32 bits on each clock edge at a clock rate of 33 MHz, so the theoretical maximum bandwidth is 32 bits * 33 MHz = 132 MB/s. b. (2 points) The arbitration scheme used on the bus is called “round robin”, whereby each of the devices can have access to the bus one at a time. So, if there are three devices on the bus, then device A is given access to the bus first, then device B, and finally device C. When it is finished, device A is given the bus again. Given this scheme, what is the worst-case latency of this bus i.e. how long would A have to wait before it could become the bus master? Answer: Since the data phase can be of any length, there is no requirement that A relinquish the bus and therefore the worst-case delay for A to become the bus master again is infinite. c.
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hw5_sol - EE108B Winter 2003-2004 Handout #? Homework #5...

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