Future_Devices_Part2

Future_Devices_Part2 - High Mobility NMOS Weakly quantized...

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Unformatted text preview: High Mobility NMOS Weakly quantized Strongly quantized Main question •  Will high mobility provide high performance? ΔEg Problems ΔEg Tbody •  low density of states in the Γ-valley reduced Qinversion and hence ION Tbody Charge Quantization •  Quantization in thin films and high surface E-field Charge occupies high DOS L and X valleys with heavy mass X L •  Materials like InAs and InSb, have a much smaller band gap high leakage Γ quantization •  We have benchmarked GaAs, InAs, InSb, Ge, Si Double-Gate n-MOSFETs taking into account band structure, quantum effects, BTBT and short-channel effects. araswat! tanford 45 EE311/Future Devices Contact Number of Electrons (Qi) vs. Velocity (Vinj ) Gate TS Lg=15nm, Tox=0.7nm, VGate=0.7V, Ioff=0.1µA/µm TOX Channel Charge Qi Ts 10nm 5nm 3nm 10 5 0 Injection Velocity Vinj 10nm 5nm 3nm 4 2 Si GaAs Ion ≈ Q * vinj araswat! tanford 6 vinj (107cm/s) Qi (1012#/cm2) 15 8 InP Ge 0 InAs InSb QSi ≈ 3 x QInAs ≈ 2 x QGaAs Si GaAs InP Ge InAs InSb Vinj,InAs≈ 2xVinj,GaAs≈ 6 x Vinj,Si Kim, Krishnamohan and Saraswat, IEEE DRC 2008 46 EE311/Future Devices 1 NMOS Drive Current Body thickness (Ts) Scaling TS= 3nm 4 VDD=0.7V 5nm 4 I ON 3 10nm 2 0 Vdd Scaling Vdd 0.7V 0.5V 0.3V 0.7V 0.5V 3 2 1 1 0.3V Si GaAs InP Ge 0 InAs InSb Si GaAs InP Ge InAs InSb Lg=15nm, Tox=0.7nm, Ioff=0.1µA/um Ion ≈ Q * vinj  Higher Ion with III-Vs and Ge. III-Vs, Ge with 0.5V outperforms Si with 0.7V  Less power consumption Kim, Krishnamohan and Saraswat, IEEE DRC 2008 araswat! tanford 47 EE311/Future Devices NMOS Ioff,min BTBT (Body Thickness scaling) 10-3 5 IOFF,BTBT (A/µm) I ON-9(mA/ -µ7m) -5 -11 10 4 7nm 5nm 0.7V 3nm 0.5V 7nm 5nm Ts 3nm 0.3V ITRS Spec 10 3 10 2 1 10-13 10 ION (mA/µm) 5 10nm 5nm 3nm (mA/ µ m) 6 5 0 Si Si GaAs GaAs InP Ge Ge InAs InSb InAs InSb LG=15nm, TOX=0.7 nm, Vdd=0.7V, Ioff=0.1µA/um InAs/InSb/Ge : BTBT leakage is too high Body thickness (Ts) scaling reduces IBTBT over 1000 times. Kim, Krishnamohan and Saraswat, IEEE DRC 2008 araswat! tanford 48 EE311/Future Devices 2 “MOSFET”-like structures using III-V Main advantages of using “MOSFET”-like structures instead of MESFETs or MODFETs are reduced gate leakage and no channel doping 1 Wide Eg III-V S Using wide bandgap III-V as Insulator for a Surface Channel MOSFET High mobility, Surface Channels Advantages Disadvantages G Small Eg III-V •  Higher mobility (better •  Very high gate D G G •  interface) Simpler process (no need for high-k) •  High E-field leakage Need a lattice matched high bandgap III-V 2 Using high-k dielectric as Insulator for a Surface Channel MOSFET Advantages Disadvantages High mobility, High-k dielectric G Small Eg III-V •  Simpler process (single III- •  Worse interface S D G G •  •  V material) Slightly higher capacitance •  Low gate leakage •  High E-field 3 Wide Eg III-V S araswat! tanford •  Using high-k dielectric as Insulator for a Center Channel MOSFET Advantages High mobility, Center Channel G •  Very high mobility Small Eg III-V D G High-k dielectric G •  •  •  •  Zero E-field Reduced BTBT leakage Decouple high-k interface properties from transport properties Lower DIBL (for same Ts) Low gate leakage 49 properties Low surface mobility High BTBT leakage in small Eg material Higher DIBL in higher ε (or k) semiconductor Disadvantages •  Tighter thickness (Ts) control of III-V layers is necessary (for same short channel control) EE311/Future Devices Effect of Straining on III-V NMOS GaAs (001) : Biaxial Tensile Strain (BiT) In0.25Ga0.75As (001) Uniaxial Compressive Strain (UniC) In0.75Ga0.25As (111) Biaxial Compressive Strain (BiC) Si (001) Biaxial Tensile Strain (BiT) No Strain: In0.25Ga0.75As is the Best Strain : GaAs, In0.75Ga0.25As can evenly perform araswat! tanford Kim, Krishnamohan and Saraswat, IEEE SISPAD 2008 50 EE311/Future Devices 3 del Alamo: InAs QuantumWell FETs with tch=5 nm InGaAs Schottky Gate HEMT Kim, IPRM 2010 del Alamo: InAs QuantumdelWell FETs with t =5 nm Alamo: InAs Quantumch 1.0 0.8 Well FETs with tch=5 nm ID [ mA/mm ] Kim, IPRM 2010 1E-3 0.6 1E-3 0.4 0.4 VGS = 0.1 V VGS = 0.1 V 0.2 VDS = 0.5 V VDS = 0.05 V VDS = 0.05 V 1E-4 =0V GS VGS = 0 V 0.2 0.2 0.4 0.4 VDS VDS [V][V] 0.6 0.6 0.8 0.8 tch=5 nm: n,Hall = 9,950 cm2/V.s, tch=5 nm: µµn,Hall = 9,950 cm /V.s, ION 414 µA/µm (@Ioff=100 nA/µm) ION==414 µA/µm (@Ioff=100 nA/µm) 2 0.2 0.4 VDS [V] 0.6 0.8 1E-6 1E-7 1E-8 LG = 40 nm -0.4 -0.2 0.0 VGS [V] 0.2 0.4 0.6 29 Key Concerns: Gate leakage Scalability 1E-71E-7 1E-81E-8 VDS = 0.5 V VDS = 0.05 V 1E-5 VGS = 0 V 1E-9 tch=10 nm: µn,Hall = 13,500 cm2/V.s, -0.6 ION= 403 µA/µm MSD Annual Review, May 2010 1E-6 1E-6 tch = 5 nm InAs HEMT tch = 10 nm InAs HEMT 1E-4 VGS = 0.1 V tch=5 nm: µn,Hall = 9,950 cm2/V.s, ION= 414 µA/µm (@Ioff=100 nA/µm) VDS = 0.5 V tch = 10 nm InAs HEMT 1E-5 ID [ A/ m ] V 0.0 1E-4 tch = 5 nm InAs HEMT tch = 5 nm10 nm InAs HEMT tch = InAs HEMT 1E-5 0.2 0.0 0.0 0.0 0.4 0.0 0.0 VGS = 0.3 V VGS = 0.3 V 0.6 1E-3 0.2 VGS = 0.5 V D ID I mA/mm ] ] [ [ mA/mm 0.8 VGS = 0.5 V 0.6 ID [ A/ m ] 0.8 tch = 5 nm InAs HEMT t = 5 10 InAs HEMT tch ch = nmnm InAs HEMT tch = 10 nm InAs HEMT LG = 40 nm LG = 40 nm ID [ A/ m ] 1.0 VGS = 0.5 V LG = 40 nm VGS = 0.3 V Kim, IPRM 2010 1.0 tch = 5 nm InAs HEMT tch = 10 nm InAs HEMT L nm LG = 40G = 40 nm 1E-91E-9 tch=10 nm: µn,Hall 13,500 cm2/V.s, tch=10 nm: µn,Hall = = 13,500 cm2/V.s, -0.6 -0.6 -0.4 -0.2 0.0 -0.4 -0.2 0.0 0.2 0.2 0.4 ION==403 µA/µm ION 403 µA/µm MSD Annual Review, May May 2010 MSD Annual Review, 2010 VVGS GS [V] [V] V GS araswat! tanford 0.4 0.6 29 0.6 29 29 J. A. del Alamo (MIT) 29 51 EE311/Future Devices ALD Al2O3/In0.65Ga0.35As MOSFETs In0.65Ga0.35As MOSFETs with ALD Al2O3 ! I-V Characteristics ! Device Structure !"#$%&'()*+,"" 01#22345*67!2('8)-#('.)+9 -"%('.)*/,"" Y. Xuan et al., (Purdue) EDL 29, 295 (2008) "3 %*&:))(*;"<,='9 Y. Xuan et al., EDL 29, 295 (2008) Key problems: Surface passivation, contact resistance, integration on Si araswat! tanford MSD Annual Review, May 2008 52 24 EE311/Future Devices 4 29 In0.7Ga0.3As Quantum-Well FET on Si Substrate Datta, et al., (Intel), IEEE EDL, August 2007! araswat! tanford 53 EE311/Future Devices Compound Semiconductor on Insulator (XOI) Javey: Compound Semiconductor on Insulator (XOI) Javey: Compound Semiconductor •  InAs XOI FETs (Lg=0.5 µm) on Insulator InAs thickness: 20 nm •  (XOI) XOI FETs (Lg=0.5 µm) thickness: 20 nm e oxide: 8 nm ZrO2 1E-3 1E-6 0.4 0.6 VGS (V) 1E-8 1E-3 1E-4 800 0.2V 600 VDS=0.1V VDS=0.3V-0.2V VDS=0.5V-0.6V 400 200 1E-7 -1V 0.8 1.0 0.6V 1000 IDS ( A/ m) IDS (A/ m) 1E-5 1V 1200 1E-4 -0.2V -0.6V 0.2 1400 0 0.0 -1.0 IDS (A/ m) 1V 0.6V 0.2V •  Gate oxide: 8 nm ZrO2 • InAs XOI FETs (Lg=0.5 µm) • InAs thickness: 20 nm • Gate oxide: 8 nm ZrO2 -0.5 0.2 0.4 0.6 VGS (V) 0.0 0.5 1E-5 VDS=0.1V VDS=0.3V VDS=0.5V 1E-6 1E-7 -1V 0.8 1.0 1E-8 -1.0 -0.5 0.0 VGS (V) 0.5 1.0 1.0 VGS approach for III-V heterostructure fabrication with thin buffer layer on Si Significance: promising(V) Significance: promising approach for III-V heterostructure fabrication with thin buffer layer on Si MSD Annual Review, May 2010 ificance: promising approach for III-V heterostructure araswat! tanford brication with thin buffer layer on Si MSD Annual Review, May 2010 13 Ali Javey (UC Berkeley) 54 13 13 EE311/Future Devices 13 5 1 30 [001] GaSb GaAs 4 3 60 Uniaxial (100) (100) [010] Biaxial µstrain/µunstrained 60 2 [010] µstrain/µunstrained 90 [010] Modeling pMOS : Strain [001] 30 2 [001] 1 Biaxial Strain 0 Open - 2% Tensile Closed - 2% Comp. InSb GaSb GaAs 1600 1200 2 µh(cm /Vs) • Compression better than tension •  2.2X increase with 2% biaxial compression •  4.1X increase with 2% uniaxial compression 800 400 Tensile -2 -1 Compressive 0 1 2 Biaxial Strain (%) Compressively strained Sb s optimum for high µh * A. Nainani et. al. SISPAD 09/10 araswat! tanford 55 Proposal for research EE311/Future Devices Hole Mobility in MOSFETs: Experimental Buried channel Surface channel 500 0.7% Strain 400 400 300 300 200 100 0 0 200 12 2.0x10 araswat! Unstrained Si & Ge 100 Unstrained Si & Ge 12 4.0x10 2 12 6.0x10 12 8.0x10 NS (/cm ) tanford Silicon 1.7% Strain 0 0 100% 500 Ge 600 Silicon 50% Ge µh (cm2/Vs) 600 In.35Ga.65Sb (surface) 700 2 GaSb (ND= 5x10 /cm ) 400% 17 In.35Ga.65Sb (buried) 800 In.20Ga.80Sb (surface) 700 µh (cm2/Vs) 900 In.20Ga.80Sb (buried) 800 300% 900 12 2.0x10 12 4.0x10 2 12 6.0x10 12 8.0x10 NS (/cm ) •  No RSD or any other correction in µh extraction •  Peak µh : 910 (Buried) / 610 (Surface) A. Nainani et al. IEDM 2010 In collaboration with NRL •  Best results published so far 56 EE311/Future Devices 6 Fig 5 : (a) Ideal SB III-V MOSFET with source/drain metal right next to the gate. Practical implementations either have (b) a spacer between the gate and source/drain metal which causes an underlap which limits the ON current (c) an intentional overlap between the gate and the source/drain metal which introduces extra Cgs Fig. 4 Band diagram of metal contact to n-type (high Schottky barrier) and p-type GaSb (ohmic contact) Fig. 6 Scaling of IDSAT w.r.t. LG for devices of 2µm, 0.5µm underlap Fig. 7 Transfer characteristics of Schottky pMOSFETs, LG=25µm, TAl2O3=10nm Fig. Contact S MOS 9 of p Sb-based Schottkyand Comparisonlayer.chottky pMOSFETs, L =100µm, w w/o barrier Introduction of barrier layer Fig. 6 Scaling of IDSAT w.r.t. LG for devices of 2µm, 0.5µm underlap ID-VD Al G Fig. 7 Transfer characteristics leakage through substrate. effectively reduce the off-state of Schottky pMOSFETs, TAl2O3=10nm LG=25µm, Fig. 9 Comparison of Schottky pMOSFETs, LG=100µm, w and w/o barrier layer. Introduction of barrier layer Hole Mobility reduce the off-state leakage through substrate. effectively Al O 23 FigPt . 1 AFM measured root Pt mean square (rms) roughness InGaSb(7nm) of above 4.4nm on GaSb after ion implantation, 600m) RTA. AlGaSb(1.0µ C GaAs substrate Fig. 8 Output characteristics of Schottky pMOSFETs, LG=25µm, TAl2O3=14nm Fig. 3 Temperature dependence measure-ment Fig. 2 J-V characteristics of (a) Al/GaSb (b) of Al/GaSb Schottky diodes. Large (small) Fig. 11 Hole mobility - (p GaSb Ti//GaSb contacts. Contacts to n- (p-) GaSb temperature dependence for Al/nversus-)sheet charge density extracted from Fig. 10 dependence Fig. 8 show rectifying (ohmic) characteristics. Temperaturecontacts indicates high (low) Schottky barrier. Output characteristics of Schottky Schottky measurement ofHole mobility versus sheet pMOSFET, LG=100µm, Schottky pMOSFETs, Fig. 11 pMOSFETs, LG=25µm, TAl2O3=14nm LG=25µm, Al2O100hickness =14nm showing peak mobility of 640cm2/V/s LG= 3 t µm, VDS=50mV. charge density extracted from Fig. 10 Temperature dependence Schottky pMOSFET, LG=100µm, measurement of Schottky pMOSFETs, showing peak mobility of 640cm2/V/s LG=100µm, VDS=50mV. ion-implant scheme •  Non •  Overlap b/w S/D and gate Fermi level pinned near ECNL L 4 Band => low R to p-GaSb Fig. ow ΦBPdiagram of cmetal contact to araswat! n-type (high Schottky barrier) and tanford p-type GaSb (ohmic contact) Ze Yuan et al., DRC 2011 (Accepted) Fig 5 : (a) Ideal SB III-V MOSFET with source/drain metal right next to the gate. Practical implementations either have (b) a spacer between the gate and source/drain 57 E311/Future Devices metal which causes an underlap which limits theEON current (c) an intentional overlap between the gate and the source/drain metal which introduces extra Cgs Scaling Subthreshold Slope ID VT Fig. 6 Scaling of IDSAT w.r.t. LG for devices of 2µm, 0.5µm underlap Fig. 7 Transfer characteristics of Schottky pMOSFETs, LG=25µm, TAl2O3=10nm Fig. 9 Comparison of Schottky pMOSFETs, LG=100µm, 60 w/o barrier layer. Introduction of barrier layer w 60 mv/decade and effectively reduce the off-state leakage through substrate. S < 60 mv/decade VG [ NTRS/ITRS data, Plummer et al, Proc. IEEE (Mar 2001) ] VDD is scaled for low power,delay VT must scale to maintain ID In MOSFET subthreshold slope is limited to kT/q (60mV/dec at 300K) ID leakage increases •  Static power increases •  Dynamic-Logic circuits/ latches can lose value Fig. 10 Temperature dependence Fig. 8 Output characteristics of Schottky araswat! Can we the ‘60mV/dec limit’? pMOSFETs, LG=25µm, TAl2O3=14nm beat measurement of Schottky pMOSFETs, LG=10058 VDS=50mV. µm, tanford Fig. 11 Hole mobility versus sheet charge density extracted from Schottky pMOSFET, LG=100µm, 2 Eshowing peak mobility of 640cm /V/s E311/Future Devices 7 Novel Devices that can beat ‘kT/q’ Log (IDS) ID-Vg characteristics MOSFET Operation Range (VDD) 60mV/dec Lower Operation Range (VDD) VGS 0 Novel Devices with Sub-threshold Slope (SS) <60mV/dec Lower Operating Vdd Lower Power Dissipation araswat! tanford 59 EE311/Future Devices Tunneling FET EC EV(Ge) EV(Si) araswat! tanford Tunneling-controlled Injection: Small Eg and mtunnel = High Drive Currents TFETs can exhibit Sub-threshold Slope (SS) <60mV/dec Ambipolar conduction a problem 60 EE311/Future Devices 8 Quasi Double-gate Strained-Ge Heterostructure Tunneling FET Experimental Simulations DG Strained-Ge TFET 1E ­03 1E ­07 ID(A/µm) 1E ­05 Ion>350µA/µm 1E ­05 ID(A/µm) 1E ­03 1E ­07 1E ­09 Vds=0.5V Vds=1V V 0.5V (s-Ge, Simul) Vds=3V Vds=1V (DGFET, s ­Ge, imul ) VDS=1V (s-Ge, SSimul) Vds=5V Vds=3V (DGFET, s ­Ge, imul ) VDS=3V (s-Ge, SSimul) Vds=5V (DGFET, s ­Ge, imul ) VDS=5V (s-Ge, SSimul) Vds=0.5V (DGFET, s ­Ge, Simu l) DS= 1E ­09 1E ­11 1E ­11 SS~50mV/dec 1E ­13 1E ­13 0 0 1 2 3 4 1 2 5 3 Vgs(V) 4 5 Vgs(V) EC EV(Ge) EV(Si) Krishnamohan, Kim, Raghunathan & Saraswat. IEEE IEDM, 2008 •  Subthreshold slope of ~50 mV/dec at VDS< 1 V •  Record high drive currents ~ 300 µA/µm at VDS=4 V araswat! •  Due to small band-gap of Ge and double-gate electrostatics. tanford 61 EE311/Future Devices Seemingly Useful Devices Limited Current Drive Cryogenic operation Limited Fan-Out Critical dimension control Challenging fabrication and process integration B + = ~ 2 nm Spintronics Need high spin injection and long spin coherence time araswat! tanford Limited thermal stability New architectures needed 62 Carbon Nanotubes Controlled growth EE311/Future Devices 9 Carbon Nanotubes: Introduction Bandstructure E Rolled up graphene sheet conduction EF valence k|| x zig-zag tube Quasi-metal araswat! ky ! chiral tube Semiconductor armchair tube Metal 0º < θ < 30º θ = 0º tanford θ = 30º 63 EE311/Future Devices E E Nanotube Band Structure semiconducting small bandgap semiconducting 1.0 0.15 0 -10 0 Vgate (V) 10 large bandgap semiconducting G (e2/h) 0.15 G (e2/h) G (e2/h) k! metal 0 Eg ≈ 0.8/d (nm) eV)! k|| k|| k! Egap 0 0 -4 0 4 Vgate (V) 0 -10 0 Vgate (V) 10 Due to curvature, strain, etc. araswat! tanford McEuen et al., IEEE Trans. Nanotech., 1 , 78, 2002.! 64 EE311/Future Devices 10 Graphene Nano Ribbon (GNR) Share many of the fascinating properties with CNTs: •  Can carry large current densities •  Large electron mean free path •  Mechanically strong Have major differences Pros:   Lithography can be used to pattern them   Interconnects and devices may be patterned seamlessly.   Contact resistance may be smaller Cons:   Quantum resistance is twice larger   Extra electron scatterings if edges are rough => needs passivation araswat! tanford 65 EE311/Future Devices Armchair GNRs 1 2 3 4 . . Bandstructure of Graphe Nano Ribbon (GNR) N If N=3p or N=3p+1 GNR is semiconducting Armchair GNRs Conductance of Armchair GNRs N=83 W=10.20 nm 1 2 3 4 . . m-GNR N N=84 W=10.33 nm s-GNR En N=82 hv f W=10.08 nm 2W G G0 n 1 3 If N=3p+2 GNR is metallic (Solid line) E 1 f( f ( En E f ) G0 n GNR Width, W (nm) Conductance: Zigzag GNRs Zigzag GNRs If N=3p or N=3p+1 GNR is semiconducting (dashed line) Ef ) n n 11 Being off by one row of atoms can change conductance by orders of magnitude! •  Very high mobility •  Being off by one row of atoms can change conductance by orders of magnitude! •  Edges need to be passivated •  Bandgap is very small 14 E araswat! tanford hv f hv f n for n >0 Ref: A. Naeemi et al., IEEEn Interconnect Tech. Conf., June 2008. 4W 2W G G0 f ( En n 66 E f ) G0 1 f ( En n Ef ) EE311/Future Devices 13 11 Ballistic Nanotube Transistors Growth MOS Transistor Nanotube Gate HfO2 D S 10 nm SiO2 CnHm Fe CnHm p++ Si Catalyst Support P-MOSFETs 0.2 V -5 10 -6 -0.1 V IDS (µA) µ -7 10 I S ( A) D 10 -I S (A) D IDS (µA) Dai (Stanford) McIntyre (Stanford) Gordon (Harvard) Lundstrom (Purdue) -5 -10 - L ~ 50 nm -0.4 V -15 - -8 10 VDS = -0.1,-0.2,-0.3 V -9 10 -0.7 V -20 L ~ 50 nm -1.0 V -1.3 V -1.5 -1.0 -0.5 0.0 VG (V) 0.5 -25 -0.4 -0.3 -0.2 -0.1 0.0 VDS (V) Key Challenge: Low thermal budget controlled growth ! araswat! tanford 67 EE311/Future Devices I s (A) d High Performance CNT -6 10 N-MOSFETs 10 D G 10 -8 Vds=0.5 V S~70 mV/dec S~80 mV/dec -10 d~1.6 nm S Pd G HfO2 n+ i -1 K+ n+ 10 Pd 8 I s (µ A) d K+ CNT 500 nm SiO2 0 Vgs (V) p-FET 1 n-FET Moderate S/D doping 6 4 p+ Si 2 Dai/Gordon/Guo Groups 0 -0.4 -0.2 0.0 0.2 0.4 Vds (V) araswat! tanford 68 EE311/Future Devices 12 Ambipolar Behavior in Nanotube FETs SB MOS Ambipolar behavior due to Schottky contacts Dai group, Stanford araswat! tanford 69 EE311/Future Devices New Promising Developments New Promising Developments araswat! http://www.fujitsu.com/global/news/pr/archives/month/2008/20080303-01.html tanford 70 EE311/Future http://www.fujitsu.com/global/news/pr/archives/month/2008/20080303-01.html Devices 4 13 Nano-Patterning Self-Assembly Molecular Materials Molecular Electronics Molecular-Scale Three-Terminal Devices ? araswat! tanford 71 EE311/Future Devices Self-Assembled Monolayer Molecular FET Molecular Switchs! Molecular FETs ! Molecular Length Defines Channel araswat! tanford 72 EE311/Future Devices 14 Molecular Electronics Interfaced with Silicon Technology Demultiplexers Order (n) wires (large pitch) Molecular Switch! To gain element or logic circuit MS multiplexer Crosspoint molecular electronic memory: 2n bits (20 – 30 nm pitch) •  Molecular mechanical complexes as solid-state switch elements •  Non-traditional patterning techniques to achieve a memory bit (cross-point) density of >1011/cm2. •  Non-linear, voltage response of molecular switches to latch (amplify) and clock signals by coupling a large molecular circuit with very few CMOS-type amplifiers. Source: Nicholas Melosh araswat! tanford 73 EE311/Future Devices Organic Semiconductors Applications LSI (864 Transistors) •  identification tags •  low-end data storage B. Crone, A. Dodabalapur et al. Nature 403, 521 (2000) •  smart cards •  emissive displays •  electronic paper All-Printed Polymer Circuit •  distributed computing Z. Bao / Stanford •  toys, clothes, ... low-cost, lightweight, rugged, flexible electronics No competition to Si, Going where Si can‘t follow !! araswat! tanford 74 EE311/Future Devices 15 Motivation for Organic FETs 25 µm Low-Cost, Flexible Electronics Philips Plastic Logic Penn State / Sarnoff 30 µm Siemens araswat! tanford 75 EE311/Future Devices Theoretical Limits to Scaling   Thermodynamic limit: Eb ≥ kB.T.ln2 mechanics ∆x . ∆p ≥ h xmin (Integration density) ∆E . ∆t ≥ h τ (switiching speed) Emin   Quantum   Ultimate •  •  •  •    For Eb xmin limit: xmin ~ 1.5 nm 5.1013 transistors/cm2 Switching speed tmin ~ 0.04 ps 25 Tbits/sec Switching energy Ebit = 17 meV Power = 55 nW/bit densely packed, 100% duty cycle devices P= n max E bit t min •  Total power density = 4.106 W/cm2   With duty cycle ~1 %, Active transistors ~1 % •  Total power density = 370 W/cm2 araswat! tanford ! Zhirnov et al., Proc. IEEE, November 2003 76 EE311/Future Devices 16 Spin Based Switch Charge Spin ΔEb(e-) ~1.7x10-2 eV ΔE(spin) ~8.6x10-8 eV B a Eb Eb w += a w ΔE(spin) << ΔE(e-) After Mark Bohr, (Intel) Single spin state can be detected by measuring if there is any tunneling current. araswat! tanford 77 EE311/Future Devices Performance Technology Scaling Historical Trend < 15nm 22nm 45-32nm > 65nm 2010 Adapted from: 2008 IEDM Short Course, 22nm CMOS Technology araswat! tanford 78 time EE311/Future Devices 17 New materials Ge III-V Semiconductors CNT Ta2O5 HfO2 ZrO2 PtSi2 Al SiO2 SiO2 Si HSQ Si3N4 Al Air WSi2 CoSi2 Polymer Poly Si TiSi2 Low-k dielectrics Silicides Si RuO2 1970 TaN Y1 Metals Cu 1980 Electrode materials IrO2 TiN TaSi2 PZT Ferroelectrics BST W 1950 ZrSixOy Pt MoSi2 High-k dielectrics 2000 1990 2010 2020 (S. Sze, Based on invited talk at Stanford Univ., Aug. 1999) Moore’s Law increasingly relies on material innovations araswat! tanford 79 EE311/Future Devices 18 ...
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