{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

Interconnect_Scaling_part2

Interconnect_Scaling_part2 - Determination of Wire-length...

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon
1 EE311 / Interconnect Scaling 31 tanford University araswat Block A with N A gates and T A I/O Block B Block C Conservation of I/O’s T A + T B + T C = T A-to-B + T A-to-C + T B-to-C + T ABC Values of T within a block or collection of blocks are calculated using Rent’s rule, e.g., T A = k (N A ) P T ABC = k (N A + N B + N C ) P Recursive use of Rent’s rule gives wire- length distribution for the whole chip T A-to-B = T A + T B -T AB T B-to-C = T B + T C -T BC Ref: Davis & Meindl, IEEE TED, March 1998 Determination of Wire-length Distribution EE311 / Interconnect Scaling 32 tanford University araswat Why should we look at interconnects? Basics and Background Scaling Related Issues: Delay Problems Solutions Scaling Related Issues: Power Current Interconnect Technology Future options
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
2 EE311 / Interconnect Scaling 33 tanford University araswat Local: Wires whose length shrinks • S1 : AR maintained (3D shrink) • R up by α (worse) where α = scaling factor • C down by α (geometrical effect) • C down by low-k material • RC delay down as low-k However, delay going up compared to gate delay Semiglobal/Global: Length does not shrink • Much worse than local All types of signal wires delays are deteriorating wrt gate delay with scaling even with new low-k materials ! S2 Simple Scaling Scenarios Wire Cross section Scaling Scenarios Wire length Scaling Future Global Local Future Scaling Problems (Delay) EE311 / Interconnect Scaling 34 tanford University araswat Scaling of Interconnect Cross Section Dimensions ITRS ‘99 dimensions: local, semi-global, global wires Height Width Global Local Semiglobal
Background image of page 2
3 EE311 / Interconnect Scaling 35 tanford University araswat Solutions to Mitigate the Interconnect Problems Technological Solutions Material Solutions: Lower resistivity materials and lower-dielectric constant (Existing Paradigm) Future Solutions: 3-D integration and Optical Interconnects Circuit Solutions Repeaters (Existing Paradigm) Future Solutions: Low-swing signaling and near speed of light electrical interconnects Architectural/Combination Solutions EE311 / Interconnect Scaling 36 tanford University araswat Delay of a Global RC Line " L = 0.89 RC = 0.89 # K 1 K ox $ o % L 2 WH W X ox + H L S & ' ( ) * + For a distributed-parameter transmission line approximately Where K 1 is a constant which takes into account the fringing fields and is approximately equal to 2. Assume L S , W, X ox and H are equal to the smallest possible dimensions possible, dictated by the lithography and etching capabilities, and designated by λ . " L = 3.56 # K ox $ o % L 2 & 2 Saraswat and Mohammadi, IEEE Trans. Electron Dev., April, 1982
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
4 EE311 / Interconnect Scaling 37 tanford University araswat Impact of Interconnect Resistivity • Will superconductors really improve the circuit speed?
Background image of page 4
Image of page 5
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}