hw1 - University of California at Berkeley College of...

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College of Engineering Department of Electrical Engineering and Computer Sciences EECS150 J. Wawrzynek Spring 2003 Homework #1 This homework is due on Thursday Jan 30 th before lecture . Homework will be accepted in the EECS150 homework box outside 125 Cory Hall. Late homework will be penalized by 50%. No late homework will be accepted after the solution is handed out. 1. From Mano, problems: 10-13, 10-14, 10-15, 10-16 2. Implement (draw) the following using CMOS transistors. a) 3-input NAND gate. Label the inputs as a, b, and c, and the output as F. b) Y = (A(B+C))’, using only 3 n-type and 3 p-type MOS transistors: c) 2-input NAND-gate with tri-state output. Inputs a, and b are the normal NAND inputs; en controls the “state” of the output as in a tri-state buffer (these are the only signals available – if you need more then add circuitry to generate them). Use as few transistors as necessary. Label all inputs and outputs as with the symbol. a
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This note was uploaded on 11/18/2011 for the course ECE 150 taught by Professor Johnwawrzynek during the Spring '03 term at Berkeley.

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hw1 - University of California at Berkeley College of...

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