hw1sol - c F b) Y=(A(B+C))' A B C A B C Y c) 2-input...

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University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS150 J. Wawrzynek Spring 2003 Homework #1 Solutions 1. Problems from Mano's book: 10-13. (a) Four-input NAND CMOS gate A B C D A B C D Y (b) Four-input NOR CMOS gate A B C D A B C D Y
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10-14. An XNOR gate using transmission gates and inverters. TG TG B A Y 10-15. An 8-to-1 multiplexor using transmission gates and inverters. TG S0 I0 Y TG TG TG TG TG TG TG TG TG TG TG TG TG I1 I2 I3 I4 I5 I6 I7 S1 S2
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10-16. A master-slave D FF using transmission gates and inverters. TG TG D C TG TG Q' Q 2. a) 3-input NAND gate a b c a b
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Unformatted text preview: c F b) Y=(A(B+C))' A B C A B C Y c) 2-input NAND-gate with tri-state output en a b a b en' f 3. a) The circuit functions as a tri-state buffer: X Y Z b) F = a + b.c + d c) F = a ⊕ b 4. a) CLK X D Q b) X functions as a synchronous reset signal, because it resets the output to zero when it is asserted at the active edge of the clock. 5. D 0 1 Q 0 1 LD order X3 X0 0 1 0 1 LD order X2 X1 0 1 0 1 LD order X1 X2 y 0 1 0 1 LD order X0 X3 "0" D Q D Q CLK CLK CLK Notice that, since the first bit is sent to the output in the same cycle when LD is asserted, there is no need to store this first bit in a flip-flop....
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This note was uploaded on 11/18/2011 for the course ECE 150 taught by Professor Johnwawrzynek during the Spring '03 term at Berkeley.

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hw1sol - c F b) Y=(A(B+C))' A B C A B C Y c) 2-input...

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