hw3 - University of California at Berkeley College of...

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University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS150 J. Wawrzynek Spring 2003 Homework #3 This homework is due on Thursday February 13 th . Homework will be accepted in the EECS150 homework slot in the cabinet to the right of the main door into 125 Cory. Late homework will be penalized by 50%. No late homework will be accepted after the solution is posted. 1. Multi-level logic. a) Consider the following function expressed in two-level and/or form. Using algebraic manipulation, express the function in three-level or/and/or form: F = ac + ad + bc + bd + e b) Now assume that you can only use two-input and and or gates to implement this function. For both the two-level and the three-level forms, determine the cost in transistors, and the delay in terms of “gate delay”. 2. From Mano: Problems 3-1, 3-8, 3-12, 3-13, 3-14, 3-15, 3-23. 3.
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This note was uploaded on 11/18/2011 for the course ECE 150 taught by Professor Johnwawrzynek during the Spring '03 term at University of California, Berkeley.

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hw3 - University of California at Berkeley College of...

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