{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

# hw3 - University of California at Berkeley College of...

This preview shows pages 1–2. Sign up to view the full content.

University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS150 J. Wawrzynek Spring 2003 Homework #3 This homework is due on Thursday February 13 th . Homework will be accepted in the EECS150 homework slot in the cabinet to the right of the main door into 125 Cory. Late homework will be penalized by 50%. No late homework will be accepted after the solution is posted. 1. Multi-level logic. a) Consider the following function expressed in two-level and/or form. Using algebraic manipulation, express the function in three-level or/and/or form: F = ac + ad + bc + bd + e b) Now assume that you can only use two-input and and or gates to implement this function. For both the two-level and the three-level forms, determine the cost in transistors, and the delay in terms of “gate delay”. 2. From Mano: Problems 3-1, 3-8, 3-12, 3-13, 3-14, 3-15, 3-23. 3.

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

### Page1 / 3

hw3 - University of California at Berkeley College of...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online