hw4 - University of California at Berkeley College of...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS150 J. Wawrzynek Spring 2003 Homework #4 This homework is due on Thursday February 20 th . Homework will be accepted in the EECS150 homework slot in the cabinet to the right of the main door into 125 Cory. Late homework will be penalized by 50%. No late homework will be accepted after the solution is posted. 1) Based on the design of the combination lock presented in class, consider the design of a lock that accepts a three digit binary-coded-decimal (BCD) string for the combination, one digit at a time. As with the lock in class, assume that we use a separate circuit for “decoding” the combination. a) Draw the state transition diagram for the new lock. b) Show the circuit for decoding the combination (using ANDs, ORs, and Inverters) for the combination 5,7,1. c) Draw the circuit diagram for a one-hot encoded implementation of your lock. Assume that the flip-flops have reset and preset inputs. 2) Design a bit serial 2’s complementer as a Moore-style FSM with one input and
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 11/18/2011 for the course ECE 150 taught by Professor Johnwawrzynek during the Spring '03 term at University of California, Berkeley.

Page1 / 2

hw4 - University of California at Berkeley College of...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online