hw5 - University of California at Berkeley College of...

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University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS150 J. Wawrzynek Spring 2003 Homework #5 This homework is due on Thursday February 27 th . Homework will be accepted in the EECS150 homework box outside 125 Cory Hall. Late homework will be penalized by 50%. No late homework will be accepted after the solution is handed out. 1. Flip-flops and timing. a) For the circuit shown, assume that all the flip-flops initially hold logic 0. Draw the waveform that appears at point y . b) Assume the flip-flop setup time is 75ps and its clock-to-Q delay is 100ps. If the mux propagation delay is 150ps, what is the maximum clock frequency for this circuit? Q D Q D Q D 1 0 L D x y c l k c l k L D x y
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2. Logic gate timing waveforms. Below is shown the waveforms corresponding to a low-to-high and a high-to-low transition for an inverter. Draw approximate transition wavefoms for the other situations shown below. Assume that all transistors in all the gates and inverters are of the same
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hw5 - University of California at Berkeley College of...

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