# hw8sol - University of California at Berkeley College of...

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University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS150 J. Wawrzynek Spring 2003 Homework #8 Solutions 1. 2. repeat n times { repeat n times { shiftA, selectSum, shiftHI } shiftB, shiftHI, shiftLOW, reset }

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3. Cost (FF) Cost (FA) Delay Bit Serial O(n) O(1) O(n^2) Shift Add O(n) O(n) O(n) Array (Wallace- tree version) O(1) O(n^2) O(log n) 4. Let's write the product as follows: x3 x2 x1 x0 1 1 0 1 ----------- x3 x2 x1 x0 x3 x2 x1 x0 x3 x2 x1 x0 ------------------------ p7 p6 p5 p4 p3 p2 p1 p0 Then, p0 and p1 are obtained directly from x0 and x1. Let's use the carry save idea for the rest of the bits: 0 0 x3 x2 x3 x2 x1 x0 ----------- 0 c2 c1 0 (carry) s3 s2 s1 s0 (sum) x3 x2 x1 x0 0 -------------- k3 k2 k1 0 (carry) z3 z2 z1 z0 (sum) ------------------ p7 p6 p5 p4 p3 p2 (final sum with carry-propagate)
Then the final circuit is: a b ci FA co s a b ci FA co s a b ci FA co s a b ci FA co s a b ci FA co s a b ci FA co s a b ci FA co s a b ci FA co s x0 x1 0 x0 x2 0 x1 x3 0 x2 x3 x3 x1 x2 x0 p7 p6 p5 p4 p3 p2 p1 p0 0 s0 s1 c1 c2 z0 z1 z2 k3 k2 k1 5. 7-1) a) 12, 16 b) 31, 8 c) 24, 32 d) 18, 64 7-2) a) 8K bytes b) 2G bytes c) 64M bytes d) 4M bytes

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7-5) module prob75 reg en, rw; reg [3:0] in; reg [5:0] addr; wire [3:0] out;

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## This note was uploaded on 11/18/2011 for the course ECE 150 taught by Professor Johnwawrzynek during the Spring '03 term at University of California, Berkeley.

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hw8sol - University of California at Berkeley College of...

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