University of California at Berkeley
College of Engineering
Department of Electrical Engineering and Computer Sciences
EECS150
J. Wawrzynek
Spring 2003
Homework #11
This homework is due on
Thursday April 24
th
by 2pm
.
Homework will be accepted in
the EECS150 homework box outside 125 Cory Hall.
Late homework will be penalized
by 50%.
No late homework will be accepted after the solution is handed out.
1.
For the given circuit, assume that T
SHIFTER
=10ns, T
ADDER
=12ns, T
FF
(setup and clock to
Q)=2ns.
a)
What is the
unpipelined
throughput for the circuit?
b)
Draw a new version with two pipeline stages and maximum throughput.
c)
What is the new
throughput
?
What is the new
latency
?
2.
The following RTL describes one interation of a looped computation performed on a
simple processor comprising a datapath and a controller.
The computation takes
three constant inputs A, B, and C, and produces one output per iteration a bus labeled
Z.
All other “variables” in the RTL are registers:
X1
<
A,
X2
<
Y2;
Y
<
X1 * X2,
X1
<
B,
X2
<
Y1;
T
<
Y, Y
<
X1*X2;
X1
<
C,
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 Spring '03
 JOHNWAWRZYNEK
 Computer Science, Electrical Engineering, Cycle Time, Simple Processor

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