hw11sol - MAR <- X1 + INST2; MEM[MAR]...

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University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS150 J. Wawrzynek Spring 2003 Homework #11 1. a) T = 41.66 MHz b) c) T = 71.4 MHz; L = 26 ns
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2. a) b)
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3. ADD: cycle: 1 2 3 4 5 6 7 8 9 regRW 0 0 0 1 X1Sel 0 0 0 0 X1Enb 1 0 0 0 X2Sel 0 0 0 0 X2Enb 0 1 0 0 regSel 01 10 00 00 ALUcntl 00 00 00 00 YSel 0 0 0 0 YEnb 0 0 1 0 I1Enb 0 0 1 0 RCEnb 0 1 0 0 MARSel 0 0 0 0 MAREnb 0 0 1 0 memRW 0 0 0 0 PCEnb 0 0 1 0 Branch 0 0 0 0 Dispath 0 0 0 1 LDB: cycle: 1 2 3 4 5 6 7 8 9 regRW 0 0 0 0 0 1 X1Sel 0 0 0 0 0 0 X1Enb 1 0 0 0 0 0 X2Sel 0 1 0 0 0 0 X2Enb 0 1 0 0 0 0 regSel 01 00 00 00 00 00 ALUcntl 00 00 00 00 00 00 YSel 0 0 0 1 0 0 YEnb 0 0 0 1 0 0 I1Enb 0 0 0 0 1 0 RCEnb 0 1 0 0 0 0 MARSel 0 0 1 0 0 0 MAREnb 0 0 1 1 1 0 memRW 0 0 0 0 0 0 PCEnb 0 0 0 1 1 0 Branch 0 0 0 0 0 0 Dispatch 0 0 0 0 0 1
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4. add: X1 <- GPR[ra], RC <- INST1[5,4]; Y <- X1 + GPR[rb], INST1 <- MEM[MAR], PC <- PC + 1, MAR <- PC + 1; GPR[rc] <- Y, <dispatch>; sub: X1 <- GPR[ra], RC <- INST1[5,4]; Y <- X1 - GPR[rb], INST1 <- MEM[MAR], PC <- PC + 1, MAR <- PC + 1; GPR[rc] <- Y, <dispatch>; nor: X1 <- GPR[ra], RC <- INST1[5,4]; Y <- X1 NOR GPR[rb], INST1 <- MEM[MAR], PC <- PC + 1, MAR <- PC + 1; GPR[rc] <- Y, <dispatch>; ldb: X1 <- GPR[ra], RC <- INST1[5,4], INST2 <- MEM[MAR]; MAR <- X1 + INST2, INST1 <- MEM[PC + 1], PC <- PC + 1; GPR[rc] <- MEM[MAR], PC <- PC + 1, MAR <- PC + 1, <dispatch>;
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stb: X1 <- GPR[ra], RC <- INST1[5,4], INST2 <- MEM[MAR];
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Unformatted text preview: MAR &lt;- X1 + INST2; MEM[MAR] &lt;- GPR[rc], PC &lt;- PC + 1, MAR &lt;- PC + 1; INST1 &lt;- MEM[MAR]; PC &lt;- PC + 1, MAR &lt;- PC + 1, &lt;dispatch&gt;; beq: X1 &lt;- GPR[ra], INST2 &lt;- MEM[MAR]; ZERO &lt;- X1 GPR[rb], X1 &lt;- PC; if ZERO PC &lt;- X1 + INST2; PC &lt;- PC + 1, INST1 &lt;- MEM[PC + 1]; PC &lt;- PC + 1, MAR &lt;- PC + 1, &lt;dispatch&gt;; b) Registers = 1 ns GPR = 3 ns ALU = 12 ns MEM = 10 ns Mux = 1 ns Incrementer = 5 ns Zero = 4 ns add sub NOR ldb stb beq Ver1 56ns 56ns 56ns 84ns 84ns 98ns Ver2 48ns 48ns 48ns 48ns 80ns 80ns 5. 6. Cycle: 1 2 3 4 5 6 7 8 Adder1 W1, X1 W2, X2 W3, X3 W4, X4 Adder2 S1-1, Y1 S1-2, Y2 S1-3, Y3 S1-4, Y4 Adder3 S2-1, Z0 S2-2, Z1 S2-3, Z2 S2-4, Z3...
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hw11sol - MAR &amp;amp;lt;- X1 + INST2; MEM[MAR]...

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