hw03_sol

hw03_sol - LSU EE 2720-2 Homework 3 Solution Due: 19...

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Unformatted text preview: LSU EE 2720-2 Homework 3 Solution Due: 19 October 2011 Note: This assignment is based on material covered in Brown and Vranesic 2nd Edition Sec- tions 2.3 (truth tables), 2.4 (logic gates and networks), 2.5 (Boolean algebra), 2.6.1 (SoP and PoS forms; canonical forms), 2.7 (NAND and NOR networks), 2.8 (design examples). Problem 1: The Boolean expression below is from Midterm Exam 1. ( a ) Draw a logic diagram (show the gates) corresponding to the following Boolean expression. (As written, dont simplify it first.) Use AND, OR, and NOT gates. x y + x y z + y w x Solution appears below. x y z w ( b ) In the expression below xy has been factored out. Draw a logic diagram corresponding to this expression. As far as the diagram is concerned, treat the 1 as an input ( x , y , z , and w are the real inputs). Note: If this is solved correctly then something in the diagram should look foolishly wasteful. See the next part. x y (1 + z + w ) Solution appears below. x y z w 1 ( c ) The simplified form of the expression is just x y . Explain why thats much more obvious in the second diagram above (where xy was factored out) than in the first. Because theres a 1 input to an OR gate and so the output of the OR gate will be the constant 1 which is also the input to the AND gate. The OR gate could be replaced with the constant 1 but even better the OR gate and the input to the AND gate can be eliminated, leaving just x y . 1 Problem 2: The expression below is also from Midterm Exam 1. ( a ) Draw a logic diagram (show the gates) corresponding to the following Boolean expression. (As written, dont simplify it first.) Use AND, OR, and NOT gates....
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hw03_sol - LSU EE 2720-2 Homework 3 Solution Due: 19...

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