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Unformatted text preview: 1 S3C44B0X 16/32 RISC S3C44B0X 2.5V ARM7TDMI 8Kcache ; internal SRAM;LCD Controller( 256 STN LCD DMA) 2-ch UART with handshake(IrDA1.0, 16-byte FIFO) / 1-ch SIO 2-ch general DMAs / 2-ch peripheral DMAs with external request pins External memory controller (chip select logic, FP/ EDO/SDRAM controller) 5-ch PWM timers & 1-ch internal timer Watch Dog Timer 71 general purpose I/O ports / 8-ch external interrupt source RTC with calendar function 8-ch 10-bit ADC 1-ch multi-master IIC-BUS controller 1-ch IIS-BUS controller Sync. SIO interface and On-chip clock generator with PLL. S3C44B0X ARM CPU-SAMBA2 66MHZ Normal, Slow, Idle, and Stop mode 1 Little/Big endian support. 2 Address space: 32Mbytes per each bank. (Total 256Mbyte) 3 Supports programmable 8/16/32-bit data bus width for each bank. 4 Fixed bank start address and programmable bank size for 7 banks. 5 . 8 memory banks. - 6 memory banks for ROM, SRAM etc. - 2 memory banks for ROM/SRAM/DRAM(Fast Page, EDO, and Synchronous DRAM) 6. Fully Programmable access cycles for all memory banks. 7 Supports external wait signal to expend the bus cycle. 8. Supports self-refresh mode in DRAM/SDRAM for power-down. 9. Supports asymmetric/symmetric address of DRAM. Cache : • 4-way set associative ID(Unified)-cache with 8Kbyte. • The 0/4/8 Kbytes internal SRAM using unused cache memory. • Pseudo LRU(Least Recently Used) Replace Algorithm. • Write through policy to maintain the coherence between main memory and cache content. • Write buffer with four depth. • Request data first fill technique when cache miss occurs. • Low power • The on-chip PLL makes the clock for operating MCU at maximum 66MHz. • Clock can be fed selectively to each function block by software. • Power mode: Normal, Slow, Idle and Stop mode. Normal mode: Normal operating mode. Slow mode: Low frequency clock without PLL Idle mode: Stop the clock for only CPU Stop mode: All clocks are stopped • Wake up by EINT[7:0] or RTC alarm interrupt from idle mode. • 30 Interrupt sources( Watch-dog timer, 6 Timer, 6 UART, 8 External interrupts, 4 DMA , 2 RTC, 1 ADC, 1 IIC, 1 SIO ) • Vectored IRQ interrupt mode to reduce interrupt latency. • Level/edge mode on the external interrupt sources • Programmable polarity of edge and level • Supports FIQ (Fast Interrupt request) for very urgent interrupt request • 5-ch 16-bit Timer with PWM / 1-ch 16-bit internal timer with DMA-based or interrupt-based operation • Programmable duty cycle, frequency, and polarity • Dead-zone generation. • Supports external clock source. RTC : • Full clock feature: msec, sec, min, hour, day,week, month, year. • 32.768 KHz operation. • Alarm interrupt for CPU wake-up....
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This note was uploaded on 11/23/2011 for the course CS Linux taught by Professor Linfang during the Summer '06 term at Fudan University.
- Summer '06