WL-44B0开发板原理图

WL-44B0开发板原理图

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Unformatted text preview: 1 2 3 4 5 6 7 8 A B C D 8 7 6 5 4 3 2 1 D C B A Title Number Revision Size A3 Date: 12-May-2003 Sheet of File: F:\LAYOUT\ARM_DEVELOP_BOARD V1.0\ARM_DEVELOP_BOARD.Ddb Drawn By: UART UART.SCH S3C44B0X S3C44B0X.SCH DRAM-FLASHROM DRAM-FLASHROM.SCH POWER POWER.SCH USB-IDE USB-IDE.sch ETHERNET_8019 ETHERNET_8019.SCH AUDIO AUDIO.Sch 1 2 3 4 5 6 7 8 A B C D 8 7 6 5 4 3 2 1 D C B A Title Number Revision Size A3 Date: 12-May-2003 Sheet of File: F:\LAYOUT\ARM_DEVELOP_BOARD V1.0\ARM_DEVELOP_BOARD.Ddb Drawn By: T1IN 11 T2IN 10 R1OUT 12 R2OUT 9 T1OUT 14 T2OUT 7 R1IN 13 R2IN 8 V+ 2 C1+ 1 C1- 3 C2+ 4 C2- 5 V- 6 VCC 16 GND 15 U2 MAX3232C C15 0.1uF C13 0.1uF C10 0.1uF C16 0.1uF C12 0.1uF 5 9 4 8 3 7 2 6 1 P1 CONNECTOR DB9 C9 0.1uF C11 0.1uF 5 9 4 8 3 7 2 6 1 P2 CONNECTOR DB9 C14 0.1uF T1IN 11 T2IN 10 R1OUT 12 R2OUT 9 T1OUT 14 T2OUT 7 R1IN 13 R2IN 8 V+ 2 C1+ 1 C1- 3 C2+ 4 C2- 5 V- 6 VCC 16 GND 15 U1 MAX3232C VDD VDD (FEMAIL) UART Interface In 32-bit data mode be supported below, -UART2 channel with RTS/CTS-or UART0's RxD/TxD with RTS/CTS & SIO In 32-bit mode , UART0 Handshake TxD0 RxD0 nRTS0 nCTS0 nRTS0_M nCTS0_M nCTS0_M nRTS0_M TxD1 RxD1 nRTS1 nCTS1 nRTS1_M nCTS1_M nCTS1_M nRTS1_M TXD1_M TXD2_M TXD1_M TXD2_M 1 2 3 4 5 6 7 8 9 10 1 12 A B C D 12 1 10 9 8 7 6 5 4 3 2 1 D C B A Title Number Revision Size A1 Date: 12-May-20 3 She t of File: F:\LAYOUT\ARM_DEVELOP_BOARD V1.0\ARM_DEVELOP_BOARD.Ddb Drawn By: A D R 2 3 AD R2 AD R1 AD R0 A D R 2 A D R 2 1 A D R 2 0 A D R 1 9 A D R 1 8 A D R 1 7 A D R 1 6 A D R 1 5 A D R 1 4 A D R 1 3 A D R 1 2 A D R 1 A D R 1 0 A D R 9 A D R 8 A D R 7 A D R 6 A D R 5 D A T A 1 4 D A T A 1 5 D A T A 1 3 D A T A 1 2 D A T A 1 D A T A 1 0 D A T A 9 D A T A 8 D A T A 6 D A T A 7 D A T A 5 D A T A 4 D A T A 2 D A T A 3 D A T A 1 D A T A 0 AD R3 A D R 4 + C3 10uF/16V + C31 10uF/16V + C34 10uF/16V + C32 10uF/16V C18 103 C19 103 C52 104 C51 104 C50 104 C49 104 + C38 10uF/16V + C37 10uF/16V + C36 10uF/16V + C35 10uF/16V C17 103 ADDR3 1 ADDR2 2 ADDR1 3 ADDR0/GPA0 4 nCAS0 5 nCAS1 6 nCAS2:nSCAS/GPB2 7 nCAS3:nSRAS/GPB3 8 VDDIO0 9 VSSIO0 10 nBE0:nWBE0:DQM0 1 nBE1:nWBE1:DQM1 12 nBE2:nWBE2:DQM2/GPB4 13 nBE3:nWBE3:DQM3/GPB5 14 nOE 15 nWE 16 nGCS0 17 nGCS1/GPB6 18 nGCS2/GPB7 19 nGCS3/GPB8 20 VDD0 21 VSS0 2 nGCS4/GPB9 23 nGCS5/GPB10 24 nGCS6:nSCS0:nRAS0 25 nGCS7:nSCS1:nRAS1 26 SCKE/GPB0 27 SCLK/GPB1 28 nWAIT/GPF2 29 nXDREQ0/nXBREQ/GPF4 30 nXDACK0/nXBACK/GPF3 31 ExINT0/VD4/GPG0 32 ExINT1/VD5/GPG1 3 VDD1 34 VSS1 35 ExINT2/nCTS0/GPG2 36 ExINT3/nRTS0/GPG3 37 ExINT4/ISCLK/GPG4 38 ExINT5/ISDI/GPG5 39 ExINT6/ISDO/GPG6 40 AIN5 80 AIN4 79 AIN3 78 AIN2 7 AIN1 76 AIN0 75 VS ADC 74 VSSIO2 73 TOUT4/VD7/GPE7 72 TOUT3/VD6/GPE6 71 TOUT2/TCLK/GPE5 70 TOUT1/TCLK/GPE4 69 TOUT0/GPE3 68 EXTCLK 67 PLLCAP 6 EXTAL0 65 XTAL0 64 VS 2 63 VDD2 62 I CSCL/GPF0 61 I CSDA/GPF1 60 SIOTxD/nRTS1/I SLRCK/GPF5 59 SIORDY/TxD1/I SDO/GPF6 58 SIORxD/RxD1/I SDI/GPF7 57 SIOCLK/nCTS1/I SCLK/GPF8 56 ENDIAN/CODECLK/GPE8 5 OM3 54 OM2 53 OM1 52 OM0 51 nRESET 50 CLKout/GPE0 49 VSSIO1 48 VDDIO1 47 TDO 46 TDI...
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WL-44B0开发板原理图

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