ECE124A_F11_HW2

ECE124A_F11_HW2 - ECE 124A, Fall 2011, Hw#2 Prof. Kaustav...

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ECE 124A, Fall 2011, Hw#2 Prof. Kaustav Banerjee 1/4 UNIVERSITY OF CALIFORNIA, SANTA BARBARA Department of Electrical and Computer Engineering ECE124A VLSI Principles Homework #2 Due Date: Oct 7 th by 5:00pm Problem 1 (A) Read the slides from Intel: “ From Sand to Silicon ” and “ From Sand to Circuit ”(on the course website ) and write one page of review. (B) Based on reading, briefly describe the process of how an NMOS transistor is made on a clean wafer by figures like below. Substrate => ?? => S u b s t r a t e O x i d e => ?? => S u b s t r a t e G D B S Problem 2, Part I Consider a four-variable expression F(A,B,C,D) given by ( , , , ) F A B C D ABCD ABCD ABCD ABCD ABCD      (A) Simplify the expression F into OR-AND-INVERT circuits by using Karnaugh map. (B) Sketch a transistor-level schematic for a single-stage CMOS logic gate for expression F. (C) Sketch a stick diagram for expression F. Problem 2, Part II (Lab) (D) Simulate the following three cases for expression F using HSPICE. Assume NMOS and PMOS are unit size for all transistors, VDD =1.5V, and the operating temperature is 50 oC . Write your own HSPICE code and use
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This note was uploaded on 11/28/2011 for the course ECE 124A taught by Professor Benerjee during the Fall '08 term at UCSB.

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ECE124A_F11_HW2 - ECE 124A, Fall 2011, Hw#2 Prof. Kaustav...

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