ECE124A_F11_HW3

ECE124A_F11_HW3 - ECE 124A, Fall 2011, HW#3 Prof. Kaustav...

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Prof. Kaustav Banerjee 1 UNIVERSITY OF CALIFORNIA, SANTA BARBARA Department of Electrical and Computer Engineering ECE124A VLSI Principles Homework #3 Due Date: Oct 14 th Friday by 5:00pm Problem 1 Draw the stick diagram of the circuit shown on the right. Find the Euler path from the corresponding graph for both pull-up and pull- down networks. Problem 2 (LAB) (a) Use MAX to draw the layout of 3-input static CMOS NOR gate (DO NOT USE SUE). Your layout should be DRC clean. Capture the screen of your layout and print out as your submission. (b) Draw the stick diagram of this NOR gate. Problem 3 (LAB) (a) Implement the following circuit in Hspice using .SUBCKT command (look into the Hspice manual). Do NOT use SUE to generate the netlist at this time. You need practice in HSpice Use 65nm technology with VDD=1V and use minimum size transistors for both PMOS and NMOS (size of PMOS should be 2× size of the NMOS). Get the 65 nm bulk model from http://ptm.asu.edu/ Use .subckt .end to create basic logic gates.
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This note was uploaded on 11/28/2011 for the course ECE 124A taught by Professor Benerjee during the Fall '08 term at UCSB.

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ECE124A_F11_HW3 - ECE 124A, Fall 2011, HW#3 Prof. Kaustav...

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