04378787 - RESEARCH CHALLENGES FOR ON-CHIP INTERCONNECTION...

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..................................................................................................................................................................................................................................................... R ESEARCH C HALLENGES FOR O N -C HIP I NTERCONNECTION N ETWORKS O N-CHIP INTERCONNECTION NETWORKS ARE RAPIDLY BECOMING A KEY ENABLING TECHNOLOGY FOR COMMODITY MULTICORE PROCESSORS AND S O C S COMMON IN CONSUMER EMBEDDED SYSTEMS . L AST YEAR, THE N ATIONAL S CIENCE F OUNDATION INITIATED A WORKSHOP THAT ADDRESSED UPCOMING RESEARCH ISSUES IN OCIN TECHNOLOGY, DESIGN, AND IMPLEMENTATION AND SET A DIRECTION FOR RESEARCHERS IN THE FIELD. ...... VLSI technology’s increased capa- bility is yielding a more powerful, more capable, and more flexible computing system on single processor die. The micro- processor industry is moving from single- core to multicore and eventually to many- core architectures, containing tens to hun- dreds of identical cores arranged as chip multiprocessors (CMPs). 1 Another equally important direction is toward systems on a chip (SoCs), composed of many types of processors on a single chip. Microprocessor vendors are also pursuing mixed approaches that combine multiple identical cores with different cores, such as the AMD Fusion processors combining multiple CPU cores and a graphics core. Whether homogeneous, heterogeneous, or hybrid, cores must be connected in a high-performance, flexible, scalable, de- sign-friendly manner. The emerging tech- nology that targets such connections is called an on-chip interconnection network (OCIN), also known as a network on chip (NoC), whose philosophy has been sum- marized as ‘‘route packets, not wires.’’ 2 Connecting components through an on- chip network has several advantages over dedicated wiring, potentially delivering high-bandwidth, low-latency, low-power communication over a flexible, modular medium. OCINs combine performance with design modularity, allowing the in- tegration of many design elements on a single die. Although the benefits of OCINs are substantial, reaching their full potential presents numerous research challenges. In 2006, the National Science Foundation initiated a workshop to identify these challenges and to chart a course to solve them. The conclusions we present here are the work of all the attendees of the workshop, held last December at Stanford University. All the presentation slides, posters, and videos of the workshop talks are available online at http://www.ece.ucdavis. edu/ , ocin06/program.html. John D. Owens University of California, Davis William J. Dally Stanford University Ron Ho Sun Microsystems D.N. (Jay) Jayasimha Intel Corporation Stephen W. Keckler University of Texas at Austin Li-Shiuan Peh Princeton University ....................................................................... 96 Published by the IEEE Computer Society. 0272-1732/07/$20.00 G 2007 IEEE
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We found that three issues stand out as particularly critical challenges for OCINs: power, latency, and CAD compatibility. First, the power of OCINs implemented with current techniques is too high (by a factor of 10) to meet the expected needs of future CMPs. Fortunately, a combination of circuit and architecture techniques has the potential to reduce power to acceptable levels. Second, the latency of these networks is too large, leading to performance degra-
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