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EECS-2006-158 - RAMP A Research Accelerator for Multiple...

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RAMP: A Research Accelerator for Multiple Processors John Wawrzynek Mark Oskin Christoforos Kozyrakis Derek Chiou David A. Patterson Shih-Lien Lu James C. Hoe Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley Technical Report No. UCB/EECS-2006-158 http://www.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-158.html November 24, 2006
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Copyright © 2006, by the author(s). All rights reserved. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission.
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1 RAMP: A Research Accelerator for Multiple Processors John Wawrzynek (UC Berkeley) David Patterson (UC Berkeley) Mark Oskin (U Washington) Shih-Lien Lu (Intel) Christoforos Kozyrakis (Stanford) James C. Hoe (CMU) Derek Chiou (UT Austin) Krste Asanovic (MIT) I. I NTRODUCTION In 2005 there was a historic change of direction in the computer hardware industry: All microproces- sor companies announced that their future products would be single-chip multiprocessors, and that future performance improvements would rely on software-specified parallelism rather than additional software- transparent parallelism extracted automatically by the microarchitecture. Several of us discussed this mile- stone at the ISCA conference in June 2005. We were struck that a multibillion-dollar industry would bet their future on solving the general-purpose parallel computing problem, when so many have previously attempted but failed to provide a satisfactory approach. To tackle the parallel processing, our industry urgently needs innovative solutions that requires extensive co-development of hardware and software. However, the rate of such innovation is currently slowed by the following traditional development cycle: 1) It takes approximately four years and many millions of dollars to prototype a new architecture in hardware, even at only research quality. 2) Software engineers are ineffective until the new hardware actually shows up since simulators are too slow to support serious software development activities. Software engineers tend to innovate only after hardware arrives. 3) Feedback from software engineers based on the current production hardware cannot impact the imme- diate next generation due to overlapped hardware development cycles. Instead, the feedback loop can take several hardware generations to close fully. Hence, we conspired on how to create an inexpensive, reconfigurable, highly-parallel platform that would attract researchers from many disciplines (architecture, compilers, operating systems, applications, etc.) to work together on perhaps the biggest challenge facing computing in the past fifty years. Our goal was a platform that would allow far more rapid evolution than traditional approaches as solutions are desperately needed.
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