lect.07 - EEL 5722C Field-Programmable Gate Array Design...

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1 EEL 5722C Field-Programmable Gate Array Design Lecture 7: CAD 2: FPGA Placement (Basic) www.eecs.ucf.edu/~mingjie/EEL5722 Prof. Mingjie Lin
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2 Overview Recap + Questions & Feedbacks from the 1st lab Overall FPGA CAD flow – Logic Opt. and Technology Mapping – Placement and Routing Logic Optimization Technology Mapping Placement Research Highlight: U-Toronto VPR
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3 FPGA CAD Flow CAD I CAD II CAD III
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4 FPGA Placement: Problem Given: – A network of LUTs or CLBs resulted from your design – An FPGA chip abstracted as a network of CLBs Objective: – Find the optimal mapping with the best performance and the least of hardware cost Challenges: – Placement has a set of competing goals – Can’t optimize locally and globally simultaneously Current Status: – No optimum solution – Heuristic approaches only achieve acceptable QoS
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5 Choices of Placement Algorithms Constructive methods – begin from netlist and generate an initial placement. – Partitioning methods mincut and Kernighan-Lin methods – Clustering Incremental methods – Begin with random or constructive placement. – Iterate to improve it.
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6 Choices of Placement Algorithms Simulated annealing – Widely used today and generates best results – Can be time consuming Force-directed methods – FD relaxation – FD pairwise exchange Macro-based approaches – Genetic algorithms – Quad swaps Pairwise interchange methods
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7 Incremental/Iterative Algorithms Simulated annealing: (statistical mechanics)
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lect.07 - EEL 5722C Field-Programmable Gate Array Design...

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