lect.09 - EEL 5722C Field-Programmable Gate Array Design...

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1 EEL 5722C Field-Programmable Gate Array Design Lecture 9: CAD 3: FPGA Routing (Basic)* www.eecs.ucf.edu/~mingjie/EEL5722 Prof. Mingjie Lin * Some slides adopted from UMN EE5301 by Kia Bazargan & NWU EECS357 lectures
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2 Overview Recap + Short intro. to the 2nd lab FPGA Routing – Recap: FPGA Routing Architecture – FPGA Routing Problem Formulation Difference from conventional VLSI routing problem – Maze routing algorithm – Congestion-based negotiated routing algorithm (VPR)
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3 FPGA Architecture - Layout Island FPGAs – Array of functional units – Horizontal and vertical routing channels connecting the functional units – Versatile switch boxes – Example: Xilinx, Altera Row-based FPGAs – Like standard cell design – Rows of logic blocks – Routing channels (fixed width) between rows of logic – Example: Actel FPGAs
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4 VI-4 FPGA Programmable Switch Elements Used in connecting: – The I/O of functional units to the wires – A horizontal wire to a vertical wire – Two wire segments to form a longer wire segment
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5 FPGA Routing Channels Architecture Note: fixed channel widths (tracks) Should “predict” all possible connectivity requirements when designing the FPGA chip Channel -> track -> segment Segment length? – Long: carry the signal longer, less “concatenation” switches, but might waste track – Short: local connections, slow for longer connections channel track segment
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6 FPGA Switch Boxes Ideally, provide switches for all possible connections Trade-off: – Too many switches: Large area Complex to program – Too few switches: Cannot route signals Xilinx 4000 One possible solution
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7 VLSI Routing (NOT only FPGA) Problem – Given a placement, and a fixed number of metal layers, find a valid pattern of horizontal and vertical wires that connect the terminals of the nets – Levels of abstraction: Global routing Detailed routing
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lect.09 - EEL 5722C Field-Programmable Gate Array Design...

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