lect.12 - EEL 5722C Field-Programmable Gate Array Design...

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1 EEL 5722C Field-Programmable Gate Array Design Lecture 12: FPGA Modern Application: Logic Emulation* Prof. Mingjie Lin * CS571, Marek Perkowski @ PSU
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2 Overview Recap + Improvements to Lab – Longer intro. – FAQ list Logic emulation – History and state-of-art Technology + Topology +Signaling
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3 Logic Emulation System What? – A programmable hardware built with programmable logic (FPGA) and programmable interconnect devices – A software which automatically programs the hardware according to the circuit under design – Control HW/SW to support operation of the emulated design hardware component operating in real time Why? – Design verification issues – Real-time operation – System-level testing – Rapid prototyping
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4 Emulation at NVIDIA Mike Butts - RAMP - August, 2010 One of the largest emulation labs in the world In 1995, CEO Jensen Huang “spent $1 million, a third of the company’s cash, on a technology known as emulation, which allows engineers to play with virtual copies of their graphics chips before they put them into silicon. That allowed Nvidia to speed a new graphics chip to market every six to nine months, a pace the company has sustained ever since.” - from Forbes, 1/7/08
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5 Fun Question + Wide Imagination
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6 Purpose of LE: Specifically… Design verification issues – Simulation-based verification methods have run out of steam when chip complexity grows – Emulation is a verification technology that grows along with design size Real-time operation – Simulation requires test vector development costly and difficult • Verification depends on test vector correctness • Certain applications must be verified in real time - human perception: audio and video. – Emulation connected to actual hardware can run – real diagnostic code, OS, and applications
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7 Purpose of LE: Specifically… (cont.) System-level testing – Often the chip meets its specifications but it fails in the system – Verify the system-level interactions between the chip and other components hard to formalize. – Internal probing is impossible when the chip is fabbed
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This note was uploaded on 11/23/2011 for the course EEL 5722c taught by Professor Lin during the Spring '11 term at University of Central Florida.

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lect.12 - EEL 5722C Field-Programmable Gate Array Design...

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