lect.13 - EEL 5722C Field-Programmable Gate Array Design...

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1 EEL 5722C Field-Programmable Gate Array Design Lecture 13: FPGA Modern Application: Computer Architecture Research Accelerator* Prof. Mingjie Lin * Slides based on Hsim @ Intel, RAMP @ UCB, and FAST @ UTAustin
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2 Overview Recap + Mid-term – Problem – Understanding, understanding, understanding… FPGAs as computer architecture research accelerator – Ideas and concepts – Two case studies
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3 Architectural Modeling: A New Way of Using FPGAs Functional Emulator – Functionally equivalent to target, but does not provide any insights on design metrics Prototype (or Structural Emulator) – Logically isomorphic and functionally equivalent representation of a design Model (both Functional and Structural Emulator) – Sufficiently logically and functionally equivalent to allow estimation of design metrics of interest, e.g., performance, power or reliability
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4 Challenges of FPGA Emulation FPGAs have limited capacity Not all circuits map well into LUTs Hard to achieve resuability Solutions: – Configure FPGA into a model of the design • FPGA cycle != model cycle [RAMP Retreat 2005] • Use FPGA-optimal structures when modeling FPGA-poor structures • Offload rare but complex algorithms to software – Model composition and module library
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5 Example: Register File Target Register File with 2 Read Ports, 2 Write Ports – Reads take zero clock cycles in target – Direct configuration onto V2 FPGA: 9242 slices, 104 MHz CC 1 CC 2 rd_addr1 A C rd_val1 V(A) V(C) rd_addr2 B D rd_val2 V(B) V(D)
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6 Separating Model Clock from FPGA Clock Simulate the circuit using BlockRAM First do reads, then serialize writes Only update model time when all requests are serviced Results: 94 slices, 1 BlockRAM, 224 MHz Simulation rate is 224 / 3 = 75 MHz (FPGA-to-Model Ratio) Model CC 1 FPGA CC: 1 2 3 rd_addr1 A rd_val1 V(A) V(A) rd_addr2 B B B rd_val2 V(B)
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7 RAMP @ UCB Complete Emulation
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8 Multicore Architecture Simulation Challenge Bigger, more complex target system – Many cores, more components, cache coherence, …
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This note was uploaded on 11/23/2011 for the course EEL 5722c taught by Professor Lin during the Spring '11 term at University of Central Florida.

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lect.13 - EEL 5722C Field-Programmable Gate Array Design...

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