lect.22 - EEL 5722C Field-Programmable Gate Array Design...

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1 EEL 5722C Field-Programmable Gate Array Design Lecture 22: Crossing Clock Domain Design in FPGA* Prof. Mingjie Lin *fpga4fun.com and Lashkarian2008
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2 Overview FPGA Crossing Clock Domain – Problem and importance – Solutions – Examples
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3 Definition: Clock Domain An FPGA design can use multiple clocks – Each clock forms a "clock domain" inside the FPGA, and care needs to be taken if a signal generated in a clock domain is needed in another clock domain. A section of logic where all synchronous elements (flip=flops, synchronous RAM blocks, pipelined multipliers) are clocked by the same net (clock). – Phase coherency not required for all the clocks in the same net – Offset may be between the rising edge of clocks that are on the same net – all have the same frequency and duty cycle.
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4 Example Diagram
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5 Why Crossing Clock Domains Challenging? The error patterns and failures are not easily repeatable. Typical setup: external clock source with random phase. Failures are technology dependent. Often higher speed
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lect.22 - EEL 5722C Field-Programmable Gate Array Design...

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