lect.26 - 1 EEL 5722C Field-Programmable Gate Array Design...

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Unformatted text preview: 1 EEL 5722C Field-Programmable Gate Array Design Lecture 26: Hardware/Software Co-Design * Prof. Mingjie Lin * Grattan et. Al. d2002 2 Overview • What is and Why Reconfiguration? • Applications • Architecture in the past • New Architecture Trends • Hardware-Software Co-Design and Development • Future 3 What is Reconfiguration ? • The ability to change the hardware entity as warranted by an application – Blurs the traditional boundaries between hardware and software. • Who will like Reconfigurable Computing ? – One who enjoys real-time design and applications – One with a pioneering spirit to learn more on software and knowledgeable about hardware (or vice versa) – One who likes to produce a challenging hardware/software solutions to an application 4 Why Reconfigurable Hardware? • The one-to-one match of application to a fixed architecture is difficult and we cannot achieve high throughput • Greater functionality can be achieved with a reconfigurable logic – Lower system cost – Evaluate in terms of lifetime system costs to determine the savings – The ability to provide for high fault tolerance in the system • Reduced time-to-market – Flexible logic and on-the field reprogrammable 5 Types of Reconfiguration • Processor Reconfiguration – Changing the internal hardware capabilities(Data Path- Word size, Pipelining, Communication among Multiple Data Path Units, etc.) • Communication Reconfiguration – A set of communication channels provided in run-time for a pair of processors • Control Reconfiguration – Changes the way in which instructions streams are processed on a processor (SIMD, MIMD, MSIMD) 6 Introduction – HW/SW Partitioning • Hw/sw partitioning can speedup software – Shown by numerous researchers • E.g., Balboni, Fornaciari, Sciuto CODES’96; Eles, Peng, Kuchchinski, Doboli DAES’97; Gajski, Vahid, Narayan, Gong Prentice-Hall 1997; Grode, Knudsen, Madsen DATE’98; many others – 1.5 to 10x common – Some examples like image processing get 100-800x speedup • E.g., Cameron project, FCCM’02 • Can reduce energy too – E.g. • Henkel, Li CODES’98 • Wan, Ichikawa, Lidsky, Rabaey CICC’98 • Stitt, Grattan, Villarreal, Vahid FCCM’02 – 60-80% energy savings measured on real single-chip uP/FPGA devices 7 Intuition of Benefits – Sorting Example • Suppose desired behavior fills a buffer, sorts the buffer, and transmits the sorted list Fill() Sort() Transmit() • Sort() in software –QuickSort – Simple and fast in sw – Poor in hw, can’t be parallelized well • Sort() in hardware – Parallel Mergesort – Very fast in hardware – Slow in sw (if sequential) due to overhead • Derive one from the other?...
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This note was uploaded on 11/23/2011 for the course EEL 5722c taught by Professor Lin during the Spring '11 term at University of Central Florida.

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lect.26 - 1 EEL 5722C Field-Programmable Gate Array Design...

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