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Unformatted text preview: 1 EEL 5722C FieldProgrammable Gate Array Design Lecture 5+6: CAD I: Technology Mapping www.eecs.ucf.edu/~mingjie/EEL5722 Prof. Mingjie Lin 2 Overview • Recap + Questions & Feedbacks from the 1st lab • Overall FPGA CAD flow – Logic Opt. and Technology Mapping – Placement and Routing • Logic Optimization • Technology Mapping • Research Highlight: Berkeley ABC and UToronto VPR 3 FPGA: Fundamental Concept 4 FPGA CAD Flow CAD I CAD II CAD III 5 FPGA Logic Synthesis 6 FPGA Synthesis: Preliminaries • We focus only on combinational logic – A two or multilevel network of logic gates – contains both structural and functional information • Representation of Structural Information – Combinational logic <> directed acyclic graph (DAG) – Each node is a logic gate or a primary input/output • Representation of Functional Information – Each gate or each internal node associated with a Boolean function – Simple gate (XOR, INV, OR,…) or complicated gate 7 Example: Logic Network • network is a direct acyclic graph Primary inputs (PIs) Primary outputs (POs) Internal nodes 8 Representation of Structural Information • Directed edge indicates that the output of a gate connects to the input of another gate • A primary input (PI) node has no fanin and a primary output (PO) node has no fanout, and a node with both fanins and fanouts is an internal node 9 Various Ways to Specify a Logic Function 10 FPGA Synthesis: Problem Formulation • LUT logic synthesis : given a multilevel network of logic gates, combinational logic synthesis transforms it into a network of LUTs – each of no more than K inputs (denoted KLUT) where K is determined by the target FPGA technology • Twostep Process – logic optimization (LO): transforms a gate network into another network suitable for mapping into a network of LUTs – Technology mapping (TM): find the optimal way that covers the network with KLUTs 11 Logic Optimization (1 Lecture) 12 Logic Optimization • Origin of Problem : for any given network, there are often many equivalent Kmappable networks • The goal : transform the given network into an equivalent optimized network which is more suitable for mapping into LUTs according to one or several mapping objectives • The minimum requirement : the resulting network must have a valid KLUT mapping solution (i.e., Kmappable) • The sufficient and necessary condition for a multilevel network to be Kmappable : every node has a Kfeasible cone 13 0 4 12 8 1 1 5 13 1 9 1 3 7 1 15 1 11 1 2 6 14 10 1 0 4 12 8 1 1 5 1 13 1 9 1 3 7 1 15 1 11 2 6 14 10 Example: Synthesize a TwoOutput Function Need four products: P1, P2, P3, P4 F1 A B C D F2 A B C D 14 #1: TwoLevel ANDOR Implementation A B C D F1 F2 P1 P2 P3 P4 INPUTS AND OR 15 INPUTS NAND NAND #2: NANDNAND Implementation A B C D F1 F2 16 #3: An Improved Version A B C D F1 F2 C B D D A OAI21 (4) NAND3 (4) NAND3 (4) NAND2 (3) NAND2 (3) (2) (2) 17 Logic Optimization: Objectives & Optimality...
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 Spring '11
 LIN
 Gate, Logic gate, Fieldprogrammable gate array, logic network, logic optimization, LUTs

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