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mid-term - EEL5722C THE UNIVERSITY OF CENTRAL FLORIDA...

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EEL5722C THE UNIVERSITY OF CENTRAL FLORIDA SPRING SEMESTER, 2011 Campus: Orlando, FL * EEL5722C: Field-Programmable Gate Array (FPGA) Design (Time allowed: ONE hour) General Instructions: 1. Do NOT open this exam until instructed to do so. 2. There are FIVE categories of questions. Answer the easy ones first to maximize your score. 3. This exam is open-notes, but NOT open book. 4. Show all of your work on the exam to get credit. 5. Clearly indicate your answers. Name/PID: CONTINUED
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– 2 – EEL5722C 1. FPGA Architecture N inputs out LUT Figure 1: An N -input Look-Up Table. (a) (5 points) For a SRAM-based LUT(look-up table) in an FPGA, how many configura- tion bits are needed in order to implement an N -input LUT? Answer: (b) (5 points) For these many configuration bits, how many different N -input logic func- tions can your N -input LUT realize? (hint: a different configuration bit map means a different logic function.) Answer: CONTINUED
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– 3 – EEL5722C LUT LUT LUT N inputs N inputs out Figure 2: A network of two N -input LUTs and one 2-input LUT. (c) (5 points) If we connect two N -input LUTs and one 2-input LUT as shown in Figure 2, in total, how many configuration memory bits do we need?
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